參數(shù)資料
型號: BT849A
英文描述: Single-Chip Video Capture for PCI
中文描述: 單芯片的PCI視頻捕捉
文件頁數(shù): 85/141頁
文件大?。?/td> 1149K
代理商: BT849A
Brooktree
75
L848A_A
E
LECTRICAL
I
NTERFACES
I
2
C Interface
Bt848/848A/849A
Single-Chip Video Capture for PCI
I
2
C Interface
The Inter-Integrated Circuit (I
2
C) bus is a two-wire serial interface. Serial clock
and data lines, SCL and SDA, are used to transfer data between the bus master and
the slave device.
The Bt848 implements a single master I
2
C system, allowing no other I
2
C mas-
ter devices, but many slaves may be in the system. The timing for the bus will be
derived from the PCI clock which may be 33 MHz or slower. Bt848’s fixed divide
by 16 divider provides a timing resolution of 0.48
μ
S. A programmable register de-
termines the additional divide ratio to divide the clock down to 100 KHz or slower
rates. The formula for the I
2
C bit rate is as follows:
An I
2
C slave may slow down the data transfer rate even further by inserting wait
states.
The relationship between SCL and SDA is decoded to provide both a start and
stop condition on the bus. To initiate a transfer on the I
2
C bus, the master must
transmit a start pulse to the slave device. This is accomplished by taking the SDA
line low while the SCL line is held high. The master should only generate a start
pulse at the beginning of the cycle, or after the transfer of a data byte to or from the
slave. To terminate a transfer, the master must take the SDA line high while the
SCL line is held high. The master may issue a stop pulse at any time during an I
2
C
cycle. Since the I
2
C bus will interpret any transition on the SDA line during the
high phase of the SCL line as a start or stop pulse, care must be taken to ensure that
data is stable during the high phase of the clock. This is illustrated in Figure 35.
Bit Rate
16
I2CDIV
×
(
4
4
+
)
×
---------PCI Clock Rate
=
where:
I2CDIV
= Register bits in the I
2
C Data/Control Register
Figure 35. The Relationship between SCL and SDA
S
TART
S
TOP
SDA
SCL
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