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參數(shù)資料
| 型號： | BT849A |
| 英文描述： | Single-Chip Video Capture for PCI |
| 中文描述： | 單芯片的PCI視頻捕捉 |
| 文件頁數(shù)： | 67/141頁 |
| 文件大?。?/td> | 1149K |
| 代理商： | BT849A |
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Brooktree
57
F
UNCTIONAL
D
ESCRIPTION
DMA Controller
L848A_A
Bt848/848A/849A
Single-Chip Video Capture for PCI
have some headroom in the FIFO to allow for more data to enter, while the PCI ini-
tiator is waiting for the target to respond. Hence, the Bt848 monitors the FIFO Al-
most Full (FAFULL) counts. The Difference between FFULL and FAFULL
provides the necessary headroom to handle target latency. Table 12 shows the
FIFO size and FIFO Full/Almost Full counts in units of DWORDs.
Prior to the DMA controller executing the address phase of a PCI write trans-
action to process a WRITE instruction, the FIFO count value must be below the
FAFULL level. At all other times, the FIFOs must be maintained below the FFULL
level. The FIFO counters for all three FIFOs are monitored for full/almost full con-
ditions in both planar and packed modes.
Once the DMA controller begins the PCI bus transaction, it has committed to a
target DMA start address. If the FIFO overflows while it is waiting for the target to
respond, then the initiator must terminate the transaction just after the target re-
sponds. This is due to the fact that the DMA controller will have to start discarding
the FIFO data, since the target pointer and the data are out of sync. This terminat-
ing condition will be communicated to the Bt848 device driver by setting an inter-
rupt bit that indicates interfacing to unreasonably slow targets.
If an instruction is exhausted while the FIFO is in an over-run condition, the
Bt848 DMA controller will continue discarding the FIFO data during the next
pre-fetched instruction as well. If the DMA controller runs out of RISC instruc-
tions, the FIFO continues to fill up, and PCI bus access is still denied, then the
DMA controller will continue discarding FIFO data for the remainder of that scan
line. Once the Bt848 DMA controller detects the EOL control bits from the FIFO,
it will attempt to gain access to the PCI bus and resynchronize itself with the RISC
instruction EOL status bits. However, if the DMA controller is not successful in
getting control of the bus, it will keep track of the number of scan lines discarded
out of the FIFO and will resynchronize itself with the RISC program based on the
number of EOL control signals detected.
The planar mode requires that the DMA controller give priority to the Y FIFO
to be emptied first. In the case that there is a very long latency in getting access to
the PCI bus, all three FIFOs will be almost full when the bus is finally granted.
While bursting the Y data, the CrCb data is likely to overflow. Attempting to deliv-
er data from each FIFO to the bus will yield poor bus performance. Preference is
given to the Y FIFO to finish the burst write operation, and if Cr or Cb FIFOs each
reach a full condition, then the DMA controller will discard their data in parallel to
delivering the Y data.
Table 12. FIFO Full/Almost Full Counts
FIFO
Size
FFULL
FAFULL
FIFO1
70
68
64
FIFO2
35
34
32
FIFO3
35
34
32
Total
140
136
128
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相關(guān)代理商/技術(shù)參數(shù) |
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