參數(shù)資料
型號： BT849A
英文描述： Single-Chip Video Capture for PCI
中文描述： 單芯片的PCI視頻捕捉
文件頁數(shù)： 20/141頁
文件大?。?/td> 1149K
代理商： BT849A
Bt848/848A/849A
Single-Chip Video Capture for PCI
Brooktree
10
F
UNCTIONAL
D
ESCRIPTION
Pin Descriptions
L848A_A
133
REFOUT
O
Output of the AGC which drives the YREF+ and CREF+ pins.
REFOUT
O
In the Bt848Aand Bt849A, the external 30 K, 30 K, and 2 K
resistors are not required. However, the 0.1
μ
F capacitor
ground to GND is still needed (see Figure 25).
137
YREF+
I
The top of the reference ladder of the Y-ADC. This should be
connected to REFOUT.
150
YREF–
I
The bottom of the reference ladder of the Y-ADC. This should
be connected to analog ground (AGND).
151
CREF+
I
The top of the reference ladder of the C-ADC. This should be
connected to REFOUT.
157
CREF–
I
The bottom of the reference ladder of the C-ADC. This should
be connected to analog ground (AGND).
158
CLEVEL
I
An input to provide the DC level reference for the C-ADC.
This voltage should be one half of CREF+.
CLEVEL
I
In the Bt848A and Bt849A, this input is internally generated.
No external components are required.
I
2
C Interface (2 pins)
78
SCL
I/O
Serial Clock
Bus clock, output open drain.
79
SDA
I/O
Serial Data
Bit Data or Acknowledge, output open drain.
Video Timing Clock Interface (5 pins)
102
XT0I
A
Clock Zero pins. A 28.636363 MHz (8*Fsc) fundamental (or
third harmonic) crystal can be tied directly to these pins, or a
single-ended oscillator can be connected to XT0I. CMOS
level inputs must be used. This clock source is selected for
NTSC input sources. When the chip is configured to decode
PAL but not NTSC (and therefore only one clock source is
needed), the 35.468950 MHz source is connected to this port
(XT0).
103
XT0O
A
XT0I
A
In the Bt848A and Bt849A, this is the only clock source
required to decode all video formats. If only one source is
used the frequency must be 28.636363 MHz (50 ppm) and a
series resistor must be added to the layout. Alternatively, the
Bt848A and Bt849A may be configured exactly as the Bt848
(using 28.636363 and 35.468950 MHz sources).
XT0O
A
105
XT1I
A
Clock One pins. A 35.468950 MHz (8*Fsc) fundamental (or
third harmonic) crystal can be tied directly to these pins, or a
single-ended oscillator can be connected to XT1I. CMOS
level inputs must be used. This clock source is selected for
PAL input sources. If either NTSC or PAL is being decoded,
and therefore only XT0I and XT0O are connected to a crystal,
XT1I should be tied either high or low, and XT1O mustbe left
floating.
106
XT1O
A
Table 2. Pin Descriptions Grouped by Pin Function
(4 of 6)
Pin #
Pin Name
I/O
Signal
Description
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