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參數(shù)資料
| 型號： | BR24L01AFJ-W |
| 廠商： | Rohm CO.,LTD. |
| 英文描述： | 128】8 bit electrically erasable PROM |
| 中文描述： | 128】8位電可擦除可編程ROM |
| 文件頁數(shù)： | 8/26頁 |
| 文件大?。?/td> | 391K |
| 代理商： | BR24L01AFJ-W |
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BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
Memory ICs
BR24L01AFV-W / BR24L01AFVM-W
8/25
z
Device operation
1) Start condition (Recognition of start bit)
All commands are proceeded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH.
The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command
until this condition has been met. (See Fig.4 SYNCHRONOUS DATA TIMING)
2) Stop condition (Recognition of stop bit)
All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is
HIGH. (See Fig.4 SYNCHRONOUS DATA TIMING)
3) Notice about write command
In the case that stop condition is not executed in WRITE mode, transferred data will not be written in a memory.
4) Device addressing
Following a START condition, the master output the slave address to be accessed.
The most significant four bits of the slave address are the “device type identifier”, for this device it is fixed as “1010”.
The next three bit (device address) identify the specified device on the bus.
The device address is defined by the state of A0, A1 and A2 input pins. This IC works only when the device address
inputted from SDA pin correspond to the state of A0, A1 and A2 input pins. Using this address scheme, up to eight
device may be connected to the bus. The last bit of the stream (R/W - - - READ / WRITE) determines the operation to
the performed.
The last bit of the stream (R/W - - - READ / WRITE) determines the operation to be performed. When set to “1”, a read
operation is selected ; when set to “0”, a write operation is selected.
R / W set to “0” - - - - - - WRITE (including word address input of Random Read)
R / W set to “1” - - - - - - READ
A2
A1
A0
1010
R / W
5) Write protect (WP)
When WP pin set to V
CC
(H level), write protect is set for 128 words (all address).
When WP pin set to GND (L level), enable to write 128 words (all address).
Either control this pin or connect to GND (or V
CC
). It is inhibited from being left unconnected.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BR24L01 | 128】8 bit electrically erasable PROM |
| BR24L04F-W | 512】8 bit electrically erasable PROM |
| BR24L04FJ-W | 512】8 bit electrically erasable PROM |
| BR24L04FV-W | 512】8 bit electrically erasable PROM |
| BR24L04FVM-W | 512】8 bit electrically erasable PROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BR24L01AFJ-WE2 | 功能描述:電可擦除可編程只讀存儲器 SRL 128X8 BIT RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| BR24L01AFVJ-W | 制造商:ROHM 制造商全稱:Rohm 功能描述:I2C BUS 1Kbit (128 x 8bit) EEPROM |
| BR24L01AFVJ-WE2 | 功能描述:IC EEPROM SER 1KBIT I2C 8TSSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:256K (32K x 8) 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:28-TSSOP（0.465"，11.8mm 寬） 供應(yīng)商設(shè)備封裝:28-TSOP 包裝:帶卷 (TR) 其它名稱:71V256SA15PZGI8 |
| BR24L01AFVM-W | 制造商:ROHM 制造商全稱:Rohm 功能描述:128】8 bit electrically erasable PROM |
| BR24L01AFVM-WTR | 功能描述:電可擦除可編程只讀存儲器 IC 電可擦除可編程只讀存儲器 SRL 128X8BIT RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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