
The W/R values are:
Where W/R is:
0
The bq2011 outputs the requested register
contents specified by the address portion of
CMDR.
1
The following eight bits should be written
to the register specified by the address por-
tion of CMDR.
The lower seven-bit field of CMDR contains the address
portion of the register to be accessed. Attempts to write
to invalid addresses are ignored.
Primary Status Flags Register (FLGS1)
The read-only FLGS1 register (address=01h) contains
the primary bq2011 flags.
The
charge status
flag (CHGS) is asserted when a
valid charge rate is detected.
valid when V
SRO
< -400
μ
V.
400
μ
V or discharge activity clears CHGS.
Charge rate is deemed
A V
SRO
of greater than-
The CHGS values are:
Where CHGS is:
0
Either discharge activity detected or V
SRO
>
-400
μ
V
1
V
SRO
< -400
μ
V
The
battery replaced
flag (BRP) is asserted whenever
the potential on the SB pin (relative to V
SS
), V
SB
, rises
above 0.1V and determines the internal registers have
been corrupted.
The BRP flag is also set when the
bq2011 is reset (see the RST register description). BRP
is latched until either the bq2011 is charged until NAC
= LMD or discharged until EDV is reached. BRP = 1
signifies that the device has been reset.
The BRP values are:
Where BRP is:
0
bq2011 is charged until NAC = LMD or dis-
charged until the EDV flag is asserted
1
SB rising from below 0.1V, or a serial port
initiated reset has occurred
The
maximum cell voltage
flag (MCV)
whenever the potential on the SB pin (relative to V
SS
) is
above 2.0V. The MCV flag is asserted until the condi-
tion causing MCV is removed.
is asserted
The MCV values are:
Where MCV is:
0
V
SB
< 2.0V
1
V
SB
> 2.0V
The
capacity inaccurate
flag (CI) is used to warn the
user that the battery has been charged a substantial
number of times since LMD has been updated. The CI
flag is asserted on the 64th charge after the last LMD
update or when the bq2011 is reset. The flag is cleared
after an LMD update.
The CI values are:
Where CI is:
0
When LMD is updated with a valid full dis-
charge or the bq2011 is reset
1
After the 64th valid charge action with no
LMD updates
11
bq2011
FLGS1 Bits
7
6
5
4
3
2
1
0
-
-
MCV
-
-
-
-
-
FLGS1 Bits
7
6
5
4
3
2
1
0
-
-
-
CI
-
-
-
-
FLGS1 Bits
7
6
5
4
3
2
1
0
CHGS
-
-
-
-
-
-
-
FLGS1 Bits
7
6
5
4
3
2
1
0
-
BRP
-
-
-
-
-
-
CMDR Bits
7
6
5
4
3
2
1
0
-
AD6 AD5
AD4
AD3
AD2
AD1
AD0
(LSB)
CMDR Bits
7
6
5
4
3
2
1
0
W/R
-
-
-
-
-
-
-