參數(shù)資料
型號： AT91SAM9XE256-CU
廠商： Atmel
文件頁數(shù)： 96/159頁
文件大?。?/td> 0K
描述： MCU ARM9 256K FLASH 217-BGA
產(chǎn)品培訓(xùn)模塊： MCU Product Line Introduction
標(biāo)準(zhǔn)包裝： 126
系列： SAM9XE
核心處理器： ARM9
芯體尺寸： 16/32-位
速度： 180MHz
連通性： EBI/EMI，以太網(wǎng)，I²C，MMC，SPI，SSC，UART/USART，USB
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 96
程序存儲器容量： 256KB（256K x 8）
程序存儲器類型： 閃存
RAM 容量： 56K x 8
電壓 - 電源 (Vcc/Vdd)： 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 217-LFBGA
包裝： 托盤
配用： AT91SAM9XE-EK-ND - KIT EVAL FOR AT91SAM9XE
AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
2007 Microchip Technology Inc.
DS41213D-page 29
PIC16F5X
6.0
I/O PORTS
As with any other register, the I/O registers can be writ-
ten and read under program control. However, read
instructions (e.g., MOVF PORTB, W) always read the I/O
pins independent of the pin’s Input/Output modes. On
Reset, all I/O ports are defined as input (inputs are at
high-impedance), since the I/O control registers
(TRISA, TRISB, TRISC, TRISD and TRISE) are all set.
6.1
PORTA
PORTA is a 4-bit I/O register. Only the low order 4 bits
are used (PORTA<3:0>). The high order 4 bits
(PORTA<7:4>) are unimplemented and read as ‘0’s.
6.2
PORTB
PORTB is an 8-bit I/O register (PORTB<7:0>).
6.3
PORTC
PORTC is an 8-bit I/O register (PORTC<7:0>) for the
PIC16F57 and PIC16F59.
PORTC is a General Purpose Register for the
PIC16F54.
6.4
PORTD
PORTD is an 8-bit I/O register (PORTD<7:0>) for the
PIC16F59.
PORTD is a General Purpose Register for the
PIC16F54 and PIC16F57.
6.5
PORTE
PORTE is an 4-bit I/O register for the PIC16F59. Only
the high order 4 bits are used (PORTE<7:4>). The low
order 4 bits (PORTE<3:0>) are unimplemented and
read as ‘0’s.
PORTE is a General Purpose Register for the
PIC16F54 and PIC16F57.
6.6
TRIS Registers
The output driver control registers are loaded with the
contents of the W register by executing the TRIS f
instruction. A ‘1’ from a TRIS register bit puts the corre-
sponding output driver in a High-Impedance (Input)
mode. A ‘0’ puts the contents of the output data latch
on the selected pins, enabling the output buffer.
The TRIS registers are “write-only” and are set (output
drivers disabled) upon Reset.
6.7
I/O Interfacing
The equivalent circuit for an I/O port pin is shown in
Figure 6-1. All ports may be used for both input and
output operation. For input operations, these ports are
non-latching. Any input must be present until read by
an input instruction (e.g., MOVF PORTB, W). The out-
puts are latched and remain unchanged until the output
latch is rewritten. To use a port pin as output, the
corresponding direction control bit (in TRISA, TRISB,
TRISC, TRISD and TRISE) must be cleared (= 0). For
use as an input, the corresponding TRIS bit must be
set. Any I/O pin can be programmed individually as
input or output.
FIGURE 6-1:
EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
Note:
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
Data
Bus
Q
D
Q
CK
Q
D
Q
CK
P
N
WR
Port
TRIS ‘f’
Data
TRIS
RD Port
VSS
VDD
I/O
pin
W
Reg
Latch
Reset
VDD
VSS
D
Q
E
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