參數(shù)資料
型號： AT91SAM9XE256-CU
廠商： Atmel
文件頁數(shù)： 86/159頁
文件大?。?/td> 0K
描述： MCU ARM9 256K FLASH 217-BGA
產(chǎn)品培訓(xùn)模塊： MCU Product Line Introduction
標(biāo)準(zhǔn)包裝： 126
系列： SAM9XE
核心處理器： ARM9
芯體尺寸： 16/32-位
速度： 180MHz
連通性： EBI/EMI，以太網(wǎng)，I²C，MMC，SPI，SSC，UART/USART，USB
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 96
程序存儲器容量： 256KB（256K x 8）
程序存儲器類型： 閃存
RAM 容量： 56K x 8
電壓 - 電源 (Vcc/Vdd)： 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 217-LFBGA
包裝： 托盤
配用： AT91SAM9XE-EK-ND - KIT EVAL FOR AT91SAM9XE
AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
PIC16F5X
DS41213D-page 20
2007 Microchip Technology Inc.
3.6
Stack
The PIC16F54 device has a 9-bit wide, two-level hard-
ware PUSH/POP stack. The PIC16F57 and PIC16F59
devices have an 11-bit wide, two-level hardware
PUSH/POP stack.
A CALL instruction will PUSH the current value of stack 1
into stack 2 and then PUSH the current program counter
value, incremented by one, into stack level 1. If more than
two sequential CALL’s are executed, only the most recent
two return addresses are stored.
A RETLW instruction will POP the contents of stack level
1 into the program counter and then copy stack level 2
contents into level 1. If more than two sequential
RETLW
’s are executed, the stack will be filled with the
address previously stored in level 2.
For the RETLW instruction, the PC is loaded with the
Top-of-Stack (TOS) contents. All of the devices cov-
ered in this data sheet have a two-level stack. The
stack has the same bit width as the device PC, there-
fore, paging is not an issue when returning from a sub-
routine.
3.7
Indirect Data Addressing; INDF
and FSR Registers
The INDF register is not a physical register. Addressing
INDF actually addresses the register whose address is
contained in the FSR Register (FSR is a pointer). This
is indirect addressing.
EXAMPLE 3-1:
INDIRECT ADDRESSING
Register file 08 contains the value 10h
Register file 09 contains the value 0Ah
Load the value 08 into the FSR register
A read of the INDF register will return the value
of 10h
Increment the value of the FSR register by one
(FSR = 09h)
A read of the INDF register now will return the
value of 0Ah.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although Status bits may be affected).
A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 3-2.
EXAMPLE 3-2:
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
The FSR is either a 5-bit (PIC16F54), 7-bit (PIC16F57)
or 8-bit (PIC16F59) wide register. It is used in conjunc-
tion with the INDF register to indirectly address the data
memory area.
The FSR<4:0> bits are used to select data memory
addresses 00h to 1Fh.
Note:
The W register will be loaded with the
literal value specified in the instruction.
This
is
particularly
useful
for
the
implementation of data look-up tables
within the program memory.
PIC16F54: This does not use banking. FSR<7:5> bits
are unimplemented and read as ‘1’s.
PIC16F57: FSR<7> bit is unimplemented and read as
‘1’. FSR<6:5> are the bank select bits and are used to
select the bank to be addressed (00 = Bank 0,
01
= Bank 1, 10 = Bank 2, 11 = Bank 3).
PIC16F59: FSR<7:5> are the bank select bits and are
used to select the bank to be addressed
(000 = Bank 0, 001 = Bank 1, 010 = Bank 2,
011
= Bank 3, 100 = Bank 4, 101 = Bank 5,
110
= Bank 6, 111 = Bank 7).
Note:
A CLRF FSR instruction may not result in
an FSR value of 00h if there are
unimplemented bits present in the FSR.
MOVLW
H'10'
;initialize pointer
MOVWF
FSR
;to RAM
NEXT
CLRF
INDF
;clear INDF Register
INCF
FSR,F
;inc pointer
BTFSC
FSR,4
;all done?
GOTO
NEXT
;NO, clear next
CONTINUE
:
;YES, continue
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