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參數資料
| 型號： | AT89C51RB2-SLSUM |
| 廠商： | Atmel |
| 文件頁數： | 38/127頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 8051 MCU FLASH 16K 44PLCC |
| 產品培訓模塊： | MCU Product Line Introduction |
| 標準包裝： | 972 |
| 系列： | 89C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 60MHz |
| 連通性： | SPI，UART/USART |
| 外圍設備： | POR，PWM，WDT |
| 輸入/輸出數： | 32 |
| 程序存儲器容量： | 16KB（16K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
| 配用： | AT89OCD-01-ND - USB EMULATOR FOR AT8XC51 MCU AT89STK-11-ND - KIT STARTER FOR AT89C51RX2 |
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18
AT89C51RB2/RC2
4180E–8051–10/06
Table 15. CKCON0 Register
CKCON0 - Clock Control Register (8Fh)
Reset Value = 0000 000’HSB. X2’b (see Table 65 “Hardware Security Byte”)
Not bit addressable
76
54
32
1
0
-
WDX2
PCAX2
SIX2
T2X2
T1X2
T0X2
X2
Bit
Number
Bit
Mnemonic
Description
7
Reserved
6WDX2
Watchdog Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
5PCAX2
Programmable Counter Array Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
4SIX2
Enhanced UART Clock (Mode 0 and 2)
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
3T2X2
Timer 2 Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
2T1X2
Timer 1 Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
1T0X2
Timer0 Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
0X2
CPU Clock
Cleared to select 12 clock periods per machine cycle (STD, X1 mode) for CPU
and all the peripherals. Set to select 6 clock periods per machine cycle (X2
mode) and to enable the individual peripherals’X2’ bits. Programmed by
hardware after Power-up regarding Hardware Security Byte (HSB), Default
setting, X2 is cleared.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AT89C51RC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 32K Bytes Flash |
| AT89C51RC_05 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 32K Bytes Flash |
| AT89C51RC_08 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 32K Bytes Flash |
| AT89C51RC2 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 16K/ 32K Bytes Flash |
| AT89C51RC2_0312 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Microcontroller with 16K/32K Bytes Flash |
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