參數資料
型號: AT89C51ID2-SLSUM
廠商: Atmel
文件頁數: 69/157頁
文件大小: 0K
描述: IC 8051 MCU FLASH 64K 44PLCC
產品培訓模塊: MCU Product Line Introduction
標準包裝: 972
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 60MHz
連通性: I²C,SPI,UART/USART
外圍設備: POR,PWM,WDT
輸入/輸出數: 34
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 2K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
配用: AT89OCD-01-ND - USB EMULATOR FOR AT8XC51 MCU
19
AT89C51ID2
4289C–8051–11/05
Design Considerations
Oscillators Control
PwdOscA and PwdOscB signals are generated in the Clock generator and used to
control the hard blocks of oscillators A and B.
PwdOscA =’1’ stops OscA
PwdOscB =’1’ stops OscB
The following tables summarize the Operating modes:
Prescaler Divider
A hardware RESET puts the prescaler divider in the following state:
CKRL = FFh: F
CLK CPU = FCLK PERIPH = FOSCA/2 (Standard C51 feature)
CKS signal selects OSCA or OSCB: F
CLK OUT = FOSCA or FOSCB
Any value between FFh down to 00h can be written by software into CKRL register
in order to divide frequency of the selected oscillator:
CKRL = 00h: minimum frequency
F
CLK CPU = FCLK PERIPH = FOSCA/1020 (Standard Mode)
F
CLK CPU = FCLK PERIPH = FOSCA/510 (X2 Mode)
CKRL = FFh: maximum frequency
F
CLK CPU = FCLK PERIPH = FOSCA/2 (Standard Mode)
F
CLK CPU = FCLK PERIPH = FOSCA (X2 Mode)
0
1
X
0
IDLE MODE B
The CPU is off, OscB supplies the
peripherals, OscA can be disabled
(OscAEn = 0)
1X
X
1
X
POWER DOWN
MODE
The CPU and peripherals are off,
OscA and OscB are stopped
Table 20. Overview (Continued)
PCON.1
PCON.0
OscBEn
OscAEn
CKS
Selected Mode
Comment
PCON.1
OscAEn
PwdOscA
Comments
0
1
0
OscA running
1X1
OscA stopped by
Power-down mode
00
1
OscA stopped by
clearing OscAEn
PCON.1
OscBEn
PwdOscB
Comments
0
1
0
OscB running
1X1
OscB stopped by
Power-down mode
00
1
OscB stopped by
clearing OscBEn
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