參數(shù)資料
型號： AT32UC3A3-XPLD
廠商： Atmel
文件頁數(shù)： 75/94頁
文件大?。?/td> 0K
描述： KIT DEV/EVAL FOR AT32UC3A3
產(chǎn)品培訓模塊： AVR® UC3 Introduction
Sensors Xplained
標準包裝： 1
系列： AVR®32 UC3-A3 Xplained
類型： MCU
適用于相關(guān)產(chǎn)品： AT32UC3A3
所含物品： 板
77
32072SH–AVR32–10/2012
AT32UC3A3
10.1.10
AES
URAD (Unspecified Register Access Detection Status) does not detect read accesses
to the write-only KEYW[5..8]R registers
Fix/Workaround
None.
10.1.11
HMATRIX
In the PRAS and PRBS registers, the MxPR fields are only two bits
In the PRAS and PRBS registers, the MxPR fields are only two bits wide, instead of four bits.
The unused bits are undefined when reading the registers.
Fix/Workaround
Mask undefined bits when reading PRAS and PRBS.
10.1.12
TWIM
TWIM SR.IDLE goes high immediately when NAK is received
When a NAK is received and there is a non-zero number of bytes to be transmitted,
SR.IDLE goes high immediately and does not wait for the STOP condition to be sent. This
does not cause any problem just by itself, but can cause a problem if software waits for
SR.IDLE to go high and then immediately disables the TWIM by writing a one to CR.MDIS.
Disabling the TWIM causes the TWCK and TWD pins to go high immediately, so the STOP
condition will not be transmitted correctly.
Fix/Workaround
If possible, do not disable the TWIM. If it is absolutely necessary to disable the TWIM, there
must be a software delay of at least two TWCK periods between the detection of
SR.IDLE==1 and the disabling of the TWIM.
TWIM TWALM polarity is wrong
The TWALM signal in the TWIM is active high instead of active low.
Fix/Workaround
Use an external inverter to invert the signal going into the TWIM. When using both TWIM
and TWIS on the same pins, the TWALM cannot be used.
SMBALERT bit may be set after reset
The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after
system reset.
Fix/Workaround
After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer.
10.1.13
TWIS
Clearing the NAK bit before the BTF bit is set locks up the TWI bus
When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Reg-
ister (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to
attempt to continue transmitting data, thus locking up the bus.
Fix/Workaround
Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been
set.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AT32UC3A4128 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:32-bit AVR? Microcontroller
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