參數(shù)資料
型號(hào)： ASDP-21365KBC-1AA
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： SHARC Processor
中文描述： 16-BIT, 55.55 MHz, OTHER DSP, PBGA136
封裝： MO-205AE, BGA-136
文件頁數(shù)： 43/52頁
文件大?。?/td> 1320K
代理商： ASDP-21365KBC-1AA
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. A
|
Page 43 of 52
|
December 2006
SPI Interface—Slave
Table 39. SPI Interface Protocol—Slave Switching and Timing Specifications
Parameter
Timing Requirements
t
SPICLKS
t
SPICHS
t
SPICLS
t
SDSCO
Min
Max
Unit
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0
Data Input Valid to SPICLK Edge (Data Input Setup Time)
SPICLK Last Sampling Edge to Data Input Not Valid
SPIDS Deassertion Pulse Width (CPHASE = 0)
4 × t
PCLK
– 2
2 × t
PCLK
– 2
2 × t
PCLK
– 2
ns
ns
ns
2 × t
PCLK
2 × t
PCLK
2 × t
PCLK
2
2
2 × t
PCLK
ns
ns
ns
ns
ns
ns
t
HDS
t
SSPIDS
t
HSPIDS
t
SDPPW
Switching Characteristics
t
DSOE
t
DSOE
1
t
DSDHI
t
DSDHI
1
t
DDSPIDS
t
HDSPIDS
t
DSOV
SPIDS Assertion to Data Out Active
SPIDS Assertion to Data Out Active (SPI2)
SPIDS Deassertion to Data High Impedance
SPIDS Deassertion to Data High Impedance (SPI2)
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
SPIDS Assertion to Data Out Valid (CPHASE = 0)
0
0
0
0
5
8
5
8.6
9.5
ns
ns
ns
ns
ns
ns
ns
2 × t
PCLK
5 × t
PCLK
1
The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the
ADSP-2136x SHARC Processor Hardware
Reference
, “Serial Peripheral Interface Port” chapter.
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