參數(shù)資料
型號: AS3517-T
廠商: ams
文件頁數(shù): 73/94頁
文件大?。?/td> 0K
描述: IC CODEC AFE AUDIO STER 81-CTBGA
標(biāo)準(zhǔn)包裝: 2,000
類型: 音頻編解碼器
應(yīng)用: 便攜式音頻,電話
安裝類型: 表面貼裝
封裝/外殼: 81-TFBGA
供應(yīng)商設(shè)備封裝: 81-CTBGA(9x9)
包裝: 帶卷 (TR)
AS3517 V17
Data Sheet, Confidential
2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Table 75 PMU CVDD3 Register
Name
Base
Default
PMU CVDD3
2-wire serial
0x00
CVDD3 DC/DC Buck Regulator Control Register
Offset: 17h-5
This is an extended register and needs to be enabled by writing 101bto Reg. 18h first.
This register is reset at a DVDD-POR.
Bit
Bit Name
Default
Access
Bit Description
7
SKIP_OFF_CVDD3
0
R/W
Disables pulse skip mode
0: 170mA current force / pulse skip mode enabled
1: current force / pulse skip mode disabled (only ON without
load)
6
PROG_CVDD3
0
R/W
Enables settings either selected by external pin (VPRGx) or
settings stored in the 17h-5 register
0: VPRGx pins controlled
1: Register controlled
5:0
VSEL_CVDD3
00000
R/W
The voltage select bits set the DC/DC output voltage level and
power the DC/DC converter down.
00000: DC/DC powered down
01h until 38h in 50mV steps
CVDD2=0.6V+VSEL_CVDD1*50mV
(0.65V until 3.4V)
38h until 3Fh = 3.4V (no change)
Table 76 PMU Hibernate Register
Name
Base
Default
PMU Hibernate
2-wire serial
00h
PMU Hibernation Control Register (PVDD1/2, CVDD1/2/3, VLED)
Offset: 17h-6
Hibernation is started when writing to this register.
This is an extended register and needs to be enabled by writing 110b to Reg. 18h first.
This register is reset at a DVDD-POR.
Bit
Bit Name
Default
Access
Bit Description
7
0
n/a
6
KEEP_PVDD2
0
R/W
Keeps the programmed PVDD2 level during hibernation
0: power down PVDD2
1: keep PVDD2
5
KEEP_PVDD1
0
R/W
Keeps the programmed PVDD1 level during hibernation
0: power down PVDD1
1: keep PVDD1
4
KEEP_VLED
0
R/W
Keeps the 15V DC/DC step-up for backlight switched on
0: power down CVDD1
1: keep CVDD1
3
KEEP_VBUS
0
R/W
Keeps the programmed VBUS level during hibernation
0: power down CVDD2
1: keep CVDD2
2
KEEP_CVDD3
0
R/W
Keeps the programmed CVDD3 level during hibernation
0: power down CVDD3
1: keep CVDD3
1
KEEP_CVDD2
0
R/W
Keeps the programmed CVDD2 level during hibernation
0: power down CVDD2
1: keep CVDD2
0
KEEP_CVDD1
0
R/W
Keeps the programmed CVDD1 level during hibernation
0: power down CVDD1
1: keep CVDD1
Revision 1v3
74
- 93
ams
AG
Technical
content
still
valid
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