參數(shù)資料
型號： AS3517-T
廠商： ams
文件頁數(shù)： 39/94頁
文件大?。?/td> 0K
描述： IC CODEC AFE AUDIO STER 81-CTBGA
標(biāo)準(zhǔn)包裝： 2,000
類型： 音頻編解碼器
應(yīng)用： 便攜式音頻，電話
安裝類型： 表面貼裝
封裝/外殼： 81-TFBGA
供應(yīng)商設(shè)備封裝： 81-CTBGA（9x9）
包裝： 帶卷 (TR)
AS3517 V17
Data Sheet, Confidential
2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
9.2.5
USB VBUS Supply
The VBUS voltage converter consists out of a charge pump and a DCDC converter. These 2 blocks share common pins. The charge
pump (CP) and is used as USB-OTG (on the go) supply (5V/8mA) and the DCDC step-up converter provides the USB-HOST supply (5V
/500mA). Depending on the external configuration either CP mode or DCDC mode is selected. Be aware that only one block can be used
in one application. The following description shows how each block operates and how the circuit should be configured.
Additional the USB VBUS generation block features a VBUS comparator to detect different VBUS levels thus complies to SRP (session
request protocol) and HNP (host negotiation protocol).
VBUS DCDC (USB Host Supply)
With the pin USBH_CSP connected to the battery voltage the mode USB-HOST mode is selected. This means the DCDC converter
supplies 5V and up to 500mA.
For device safety an external PMOS switch is necessary in the case of a short-circuit condition on the VBUS pin. With this PMOS the
device can shut off the path between battery and output. During start-up the PMOS switch will be opened very slowly by discharging his
gate with a small current sink. Depending on the value of the Gate-Source Capacitance and the start-up time, different current values for
the current sink can be programmed.
During start-up and operation the DCDC also monitors the current over the sense resistor. If the current limit will be reached during start-
up the DCDC will generate an interrupt signal after 5.3usec de-bounce time. If this over-current condition is still present after 85s the
DCDC converter will be shut off by resetting its register. During start-up, however, an interrupt will be masked until pin USBH_PG is lower
than 1V.
Figure 27 VBUS DCDC Block Diagram
Revision 1v3
43
- 93
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Technical
content
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