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| 型號(hào)： | AS3517-T |
| 廠商： | ams |
| 文件頁(yè)數(shù)： | 25/94頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC AFE AUDIO STER 81-CTBGA |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 音頻編解碼器 |
| 應(yīng)用： | 便攜式音頻，電話 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 81-TFBGA |
| 供應(yīng)商設(shè)備封裝： | 81-CTBGA（9x9） |
| 包裝： | 帶卷 (TR) |
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AS3517 V17
Data Sheet, Confidential
2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Figure 14 Random Read
Random Read and Sequential Read are combined formats. The repeated START condition is used to change the direction after the data
transfer from the master.
The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START condition is followed
by the device-write address and the word address.
In order to change the data direction a repeated START condition is issued on the 1st SCL pulse after the acknowledge bit of the word
address transfer. After the reception of the device-read address, the slave becomes the transmitter. In this state the slave transmits
register data located by the previous received word address vector. The master responds to the data byte with a not-acknowledge, and
issues a STOP condition on the bus.
Figure 15 Sequential Read
Sequential Read is the extended form of Random Read, as more than one register-data bytes are transferred subsequently. In difference
to the Random Read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. The
number of data bytes transferred in one sequence is unlimited (consider the behaviour of the word-address counter). To terminate the
transmission the master has to send a not-acknowledge following the last data byte and generate the STOP condition subsequently.
Figure 16 Current Address Read
To keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data
transfer. The bus is idle and the master issues a START condition followed by the Device-Read address. Analogous to Random Read, a
single byte transfer is terminated with a not-acknowledge after the 1st register byte. Analogous to Sequential Read an unlimited number of
data bytes can be transferred, where the data bytes has to be responded with an acknowledge from the master. For termination of the
transmission the master sends a not-acknowledge following the last data byte and a subsequent STOP condition.
Revision 1v3
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Technical
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