參數(shù)資料
型號(hào): AS3517-T
廠商: ams
文件頁(yè)數(shù): 71/94頁(yè)
文件大?。?/td> 0K
描述: IC CODEC AFE AUDIO STER 81-CTBGA
標(biāo)準(zhǔn)包裝: 2,000
類型: 音頻編解碼器
應(yīng)用: 便攜式音頻,電話
安裝類型: 表面貼裝
封裝/外殼: 81-TFBGA
供應(yīng)商設(shè)備封裝: 81-CTBGA(9x9)
包裝: 帶卷 (TR)
AS3517 V17
Data Sheet, Confidential
2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Table 71 PMU PVDD1 Register
Name
Base
Default
PMU PVDD1
2-wire serial
00h
PVDD1 Low Drop-Out Regulator (LDO3) Control Register
Offset: 17h-1
This is an extended register and needs to be enabled by writing 001b to Reg. 18h first.
This register is reset at a DVDD-POR.
Bit
Bit Name
Default
Access
Bit Description
7
LDO_PVDD1_OFF
0
R/W
Power-down of LDO for PVDD1
0: PVDD1 (LDO3) enable
1: PVDD1 (LDO3) power-down
6
0
n/a
5
PROG_PVDD1
0
R/W
Enables settings either selected by external pins (VPRGx) or
settings stored in the 17h-1 register
0: VPRGx pins controlled
1: Register controlled
4:0
VSEL_PVDD1
00000
R/W
The voltage select bits set the LDO output in 2 different
resolution ranges
Range: 00h until 0Fh in 50mV steps
PVDD1=1.2V+VSEL_PVDD1*50mV
(1.2V until 1.95V)
Range: 10h until 1Fh in 100mV steps
PVDD1=2.0V+VSEL_PVDD1*100mV
(2.0V until 3.5V)
Table 72 PMU PVDD2 Register
Name
Base
Default
PMU PVDD2
2-wire serial
00h
PVDD2 Low Drop-Out Regulator (LDO4) Control Register
Offset: 17h-2
This is an extended register and needs to be enabled by writing 010b to Reg. 18h first.
This register is reset at a DVDD-POR.
Bit
Bit Name
Default
Access
Bit Description
7
LDO_PVDD2_OFF
0
R/W
Power-down of LDO for PVDD2
0: PVDD2 (LDO4) enable
1: PVDD2 (LDO4) power-down
6
0
n/a
5
PROG_PVDD2
0
R/W
Enables settings either selected by external pin (VPRGx) or
settings stored in the 17h-2 register
0: VPRGx pins controlled
1: Register controlled
4:0
VSEL_PVDD2
00000
R/W
The voltage select bits set the LDO output in 2 different
resolution ranges
Range: 00h until 0Fh in 50mV steps
PVDD2=1.2V+VSEL_PVDD1*50mV
(1.2V until 1.95V)
Range: 10h until 1Fh in 100mV steps
PVDD2=2.0V+VSEL_PVDD1*100mV
(2.0V until 3.5V)
Revision 1v3
72
- 93
ams
AG
Technical
content
still
valid
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