
ARM Instruction Set - Shifts
ARM7TDMI Data Sheet
ARM DDI 0029E
4-15
O
Figure 4-10: Rotate right extended
Register specified shift amount
Only the least significant byte of the contents of Rs is used to determine the shift
amount. Rs can be any general register other than R15.
If this byte is zero, the unchanged contents of Rm will be used as the second operand,
and the old value of the CPSR C flag will be passed on as the shifter carry output.
If the byte has a value between 1 and 31, the shifted result will exactly match that of
an instruction specified shift with the same value and shift operation.
If the value in the byte is 32 or more, the result will be a logical extension of the shift
described above:
1
LSL by 32 has result zero, carry out equal to bit 0 of Rm.
2
LSL by more than 32 has result zero, carry out zero.
3
LSR by 32 has result zero, carry out equal to bit 31 of Rm.
4
LSR by more than 32 has result zero, carry out zero.
5
ASR by 32 or more has result filled with and carry out equal to bit 31 of Rm.
6
ROR by 32 has result equal to Rm, carry out equal to bit 31 of Rm.
7
ROR by n where n is greater than 32 will give the same result and carry out
as ROR by n-32; therefore repeatedly subtract 32 from n until the amount is
in the range 1 to 32 and see above.
The zero in bit 7 of an instruction with a register controlled shift is compulsory; a one
in this bit will cause the instruction to be a multiply or undefined instruction.
Note
4.5.3 Immediate operand rotates
The immediate operand rotate field is a 4 bit unsigned integer which specifies a shift
operation on the 8 bit immediate value. This value is zero extended to 32 bits, and then
subject to a rotate right by twice the value in the rotate field. This enables many
common constants to be generated, for example all powers of 2.
contents of Rm
value of operand 2
31
0
carry
out
1
C
in