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參數(shù)資料
| 型號(hào)： | ARM7TDMI |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | general purpose 32-bit microprocessors |
| 中文描述： | 通用32位微處理器 |
| 文件頁(yè)數(shù)： | 191/268頁(yè) |
| 文件大?。?/td> | 1289K |
| 代理商： | ARM7TDMI |
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Debug Interface
ARM7TDMI Data Sheet
ARM DDI 0029E
8-11
O
When the instruction register is loaded with the IDCODE instruction, all the scan cells
are placed in their normal (system) mode of operation.
In the CAPTURE-DR state, the device identification code is captured by the ID
register. In the SHIFT-DR state, the previously captured device identification code is
shifted out of the ID register via the
TDO
pin, while data is shifted in via the
TDI
pin
into the ID register. In the UPDATE-DR state, the ID register is unaffected.
8.8.5 BYPASS (1111)
The BYPASS instruction connects a 1 bit shift register (the BYPASS register) between
TDI
and
TDO
.
When the BYPASS instruction is loaded into the instruction register, all the scan cells
are placed in their normal (system) mode of operation. This instruction has no effect
on the system pins.
In the CAPTURE-DR state, a logic 0 is captured by the bypass register. In the SHIFT-
DR state, test data is shifted into the bypass register via
TDI
and out via
TDO
after a
delay of one
TCK
cycle. Note that the first bit shifted out will be a zero. The bypass
register is not affected in the UPDATE-DR state. Note that all unused instruction codes
default to the BYPASS instruction.
8.8.6 CLAMP (0101)
This instruction connects a 1 bit shift register (the BYPASS register) between
TDI
and
TDO
.
When the CLAMP instruction is loaded into the instruction register, the state of all the
output signals is defined by the values previously loaded into the currently loaded scan
chain.
Note
This instruction should only be used when scan chain 0 is the currently selected scan
chain.
In the CAPTURE-DR state, a logic 0 is captured by the bypass register. In the SHIFT-
DR state, test data is shifted into the bypass register via
TDI
and out via
TDO
after a
delay of one
TCK
cycle. Note that the first bit shifted out will be a zero. The bypass
register is not affected in the UPDATE-DR state.
8.8.7 HIGHZ (0111)
This instruction connects a 1 bit shift register (the BYPASS register) between
TDI
and
TDO
.
When the HIGHZ instruction is loaded into the instruction register, the Address bus,
A[31:0]
, the data bus,
D[31:0]
, plus
nRW
,
nOPC
,
LOCK
,
MAS[1:0]
and
nTRANS
are
all driven to the high impedance state and the external
HIGHZ
signal is driven HIGH.
This is as if the signal
TBE
had been driven LOW.
In the CAPTURE-DR state, a logic 0 is captured by the bypass register. In the
SHIFT-DR state, test data is shifted into the bypass register via
TDI
and out via
TDO
after a delay of one
TCK
cycle. Note that the first bit shifted out will be a zero. The
bypass register is not affected in the UPDATE-DR state.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS1431 | Precision Adjustable Shunt Reference |
| AS1431DR4LP13 | Precision Adjustable Shunt Reference |
| AS1431DR4LP7 | Precision Adjustable Shunt Reference |
| AS1431DR4LPA | Precision Adjustable Shunt Reference |
| AS1431DR4LPB | Precision Adjustable Shunt Reference |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ARM7TDMI_G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Technical Reference Manual |
| ARM7TDMI-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:周立功的中文ARM7TDI文檔 |
| ARM920T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:System-on-Chip Platform OS Processor |
| ARM940T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TECHNICAL REFERENCE MANUAL |
| ARM946E-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ARM946E-S Microprocessor Core with Cache technical manual 6/01 |
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