參數(shù)資料
型號： AN1218
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： HC05 to HC08 Optimization
中文描述： 以HC08的優(yōu)化HC05
文件頁數(shù)： 8/56頁
文件大?。?/td> 417K
代理商： AN1218
Application Note
AN1218 Rev. 2
8
Condition Code
Register with
Overflow Bit V
A summary of the condition code register (CCR) is given below. Unless
otherwise stated, all bits correspond to both CPUs.
Overflow Bit V
This bit is set when a two's-complement overflow has occurred as the
result of an operation. The V bit has been added to the CPU08
condition code register to support two's-complement arithmetic.
Half-Carry Bit H
The half-carry bit is set when a carry has occurred between bits 3 and
4 of the accumulator because of the last ADD or ADC operation. This
bit is required for BCD operations.
Table 2. Addressing Mode Examples
Addressing Mode
Example
Inherent
RSP
Immediate
LDA
#$FF
Direct
LDA
$50
Extended
LDA
$1000
Indexed, no offset
LDA
,X
Indexed, 8-bit offset
LDA
$50,X
Indexed, 16-bit offset
LDA
$0150,X
Relative
BRA
$20
Stack Pointer, 8-bit offset
*
LDA
$50,SP
Stack Pointer, 16-bit offset
*
LDA
$0150,SP
Memory to memory
ImmDir
*
DirDir
*
Ix+Dir
*
DirIx+
*
MOV
MOV
MOV
MOV
#$30,$80
$80,$90
X+,$90
$80,X+
Indexed w/post increment
*
CBEQ
X+,LOOP
Indexed, 8-bit offset, w/post increment
*
CBEQ
$20,X+,LOOP
*
New CPU08 addressing modes
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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