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參數(shù)資料
| 型號(hào)： | AN1218 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | HC05 to HC08 Optimization |
| 中文描述： | 以HC08的優(yōu)化HC05 |
| 文件頁數(shù)： | 26/56頁 |
| 文件大?。?/td> | 417K |
| 代理商： | AN1218 |
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Application Note
AN1218 Rev. 2
26
BLE
Branch if Less Than or Equal (signed operands)
PC
←
(PC) + $0002 + Rel, if Z+(N
⊕
V)=1
i.e., if (A) _ (M), ("signed" numbers)
Operation:
Description: If the BLE instruction is executed
immediately after execution of any of the
compare or subtract instructions, the branch
will occur if and only if the two's complement
number represented by the appropriate
internal register (A, X, or H:X) was less than
or equal to the two's complement number
represented by M.
BLT
Branch if Less Than (signed operands)
PC
←
(PC) + $0002 + Rel, if (N
⊕
V)=1
i.e., if (A) < (M), ("signed" numbers)
Operation:
Description: If the BLT instruction is executed
immediately after execution of any of the
compare or subtract instructions, the branch
will occur if and only if the two's complement
number represented by the appropriate
internal register (A, X, or H:X) was less than
the two's complement number represented
by M.
New DIV
Instruction
The Divide instruction on the CPU08 does not require the lengthy code
needed to divide numbers on the CPU05. A description of the Divide
instruction is given below.
Appendix J — Five Miscellaneous CPU08
Instructions Including BCD, Divide, and CCR Operations
shows a
short example of using the new Divide instruction.
Appendix K —
CPU08 Averaging Code
illustrates an averaging routine implementing
the Divide instruction.
DIV
Divide
Operation:
(H:A) / X
→
A; Remainder
→
H
Description: Divides a 16-bit unsigned dividend
contained in the concatenated registers H
and A by an 8-bit divisor contained in index
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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