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參數(shù)資料
| 型號： | AM79Q021JC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 編解碼器 |
| 英文描述： | PCM CODEC, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 18/64頁 |
| 文件大?。?/td> | 911K |
| 代理商： | AM79Q021JC |
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SLAC Products
25
OPERATING THE QSLAC DEVICE
The following sections describe the operation of the
four independent channels of the QSLAC device. The
des cr i p ti on is va li d fo r c hann el 1 , 2, 3, or 4;
consequently, the channel subscripts have been
dropped. For example, VOUT refers to either VOUT1,
VOUT2, VOUT3, or VOUT4.
Power-Up Sequence
T he r e c o mmended Q S LAC device po w e r - u p
sequence is to apply:
1. VCC and ground
2. Signal connections and Low on RST
3. High on RST
The software initialization should then include:
1. Wait 1 ms.
2. Select
master
clock
frequency
and
source
(Commands 12 and 13). This should turn off the
CFAIL bit (Command 23) within 400
s. While the
CFAIL bit is on, normal programming can proceed,
but no channels should be activated.
3. Program filter coefficients and other parameters
as required.
4. Activate (Command 5).
If the power supply (VCCD) falls below approximately
1.0 V, the device is reset and will require complete
reprogramming with the above sequence. A reset may
be initiated by connection of a logic Low to the RST
pin, or if chip select (CS) is held low for 16 rising edges
of DCLK, a hardware reset is generated when CS
returns high. The RST pin may be tied to VCCD if it is
not used in the system.
Channel Enable Register
A channel enable register has been implemented in
the QSLAC device in order to reduce the effor t
required to address individual or multiple channels of
the QSLAC device. The register is written using MPI
Command 14. Each bit of the register is assigned to
one unique channel, bit 0 for channel 1, bit 1 for
channel 2, bit 2 for channel 3, and bit 3 for channel 4.
The channel or channels are enabled when their
corresponding enable bits are High. All enabled
channels will receive the data written to the QSLAC
device. This enables a Broadcast state (all channels
enabled) to be implemented simply and efficiently, and
multiple channel addressing is accomplished without
increasing the number of I/O pins on the device. The
Broadcast state can be further enhanced by providing
the ability to select many chips at once; however, care
must be taken never to enable more than one chip in
the Read state. This can lead to an internal bus
contention, in which excess power is dissipated. (Bus
contention will not damage the device.) Most control
comm ands defined fo r the DSLAC device are
co mp ati b le w i th the Q S LAC devic e , t h e r eb y
minimizing the impact to existing system software.
SLIC Control and Data Lines
The QSLAC device has up to five SLIC digital interface
pins per channel (CD1–C5). Each of these pins can be
programmed as either an input or an output using the
I/O Direction register (Commands 22 and 23) (see
Figure 9). The output latches can be written with
Command 20; however, only those bits programmed
as outputs will actually drive the pins. The inputs can
be read with Command 21. If a pin is programmed as
an output, the data read from it will be the contents of
the output latch. It is recommended that any of the
SLIC input/output data points, which are to be
programmed as outputs, be written to their desired
state via Command 21 before writing the data which
configures them as outputs with the I/O direction
register Command 22. This ensures that when the
output is activated, it is already in the correct state, and
will prevent unwanted data from being driven from the
SLIC output pins.
Clock Mode Operation
The QSLAC device operates with multiple clock
signals. The master clock (MCLK) is used for internal
timing including operation of the digital signal
processing and may be derived from either the MCLK
or PCLK source. The allowed frequencies are listed
under Commands 12 and 13.
The PCM clock (PCLK) is used for PCM timing and is
an integer multiple of the frame sync frequency. The
internal device clock (MCLK) can be optionally derived
from the PCLK source by setting the CMODE bit (bit 4,
Commands 12 and 13, 46/47h) to one. In this mode,
the MCLK/E1 pin is free to be used as an E1 signal
output. Clock mode options and E1 output functions
are shown in Figure 8.
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| AM79Q021JC/T | 制造商:Advanced Micro Devices 功能描述: |
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| AM79Q031JC | 制造商:Advanced Micro Devices 功能描述: |
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