參數(shù)資料
型號(hào)： AM79C976
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
中文描述： PCnet -專業(yè)⑩個(gè)10/100Mbps PCI以太網(wǎng)控制器
文件頁(yè)數(shù)： 153/309頁(yè)
文件大小： 2070K
代理商： AM79C976
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)當(dāng)前第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)第269頁(yè)第270頁(yè)第271頁(yè)第272頁(yè)第273頁(yè)第274頁(yè)第275頁(yè)第276頁(yè)第277頁(yè)第278頁(yè)第279頁(yè)第280頁(yè)第281頁(yè)第282頁(yè)第283頁(yè)第284頁(yè)第285頁(yè)第286頁(yè)第287頁(yè)第288頁(yè)第289頁(yè)第290頁(yè)第291頁(yè)第292頁(yè)第293頁(yè)第294頁(yè)第295頁(yè)第296頁(yè)第297頁(yè)第298頁(yè)第299頁(yè)第300頁(yè)第301頁(yè)第302頁(yè)第303頁(yè)第304頁(yè)第305頁(yè)第306頁(yè)第307頁(yè)第308頁(yè)第309頁(yè)
8/01/00
Am79C976
153
P R E L I M I N A R Y
INT0: Interrupt0
Offset 038h
INT0 identifies the source or sources of an interrupt.
With the exception of INTR, all bits in this register are
“
write 1 to clear
”
so that the CPU can clear the interrupt
condition by reading the register and then writing back
the same data that it read. Writing a 0 to a bit in this reg-
ister has no effect.
All bits in this register are cleared to 0 by H_RESET. In
addition, TINT, TXDNINT, TXSTRTINT, and RINT are
cleared when the RUN bit in CMD0 is cleared.
Table 59.
INT0: Interrupt0 Register
Bit
Name
Description
31
INTR
Interrupt Summary. This bit indicates that one or more of the other interrupt bits in this register are
set and the associated enable bit or bits in INTEN0 are also set. If INTREN in CMD0 is set to 1 and
INTR is set, INTA will be active. When INTR is set by SINT, INTA will be active independent of the
state of INEA.
INTR is read only. INTR is cleared by clearing all of the active individual interrupt bits that have not
been masked out.
31-28
RES
Reserved locations. Written as zeros and read as undefined.
27
LCINT
Link Change Interrupt. This bit is set when the Port Manager detects a change in the link status of
the external PHY.
26
APINT5
Auto-Poll Interrupt from Register 5. This bit is set when the Auto-Poll State Machine has detected
a change in the external PHY register whose address is stored in Auto-Poll Register 5.
25
APINT4
Auto-Poll Interrupt from Register 4. This bit is set when the Auto-Poll State Machine has detected
a change in the external PHY register whose address is stored in Auto-Poll Register 4.
24
APINT3
Auto-Poll Interrupt from Register 3. This bit is set when the Auto-Poll State Machine has detected
a change in the external PHY register whose address is stored in Auto-Poll Register 3.
23
RES
Reserved locations. Written as zeros and read as undefined.
22
APINT2
Auto-Poll Interrupt from Register 2. This bit is set when the Auto-Poll State Machine has detected
a change in the external PHY register whose address is stored in Auto-Poll Register 2.
21
APINT1
Auto-Poll Interrupt from Register 1. This bit is set when the Auto-Poll State Machine has detected
a change in the external PHY register whose address is stored in Auto-Poll Register 1.
20
APINT0
Auto-Poll Interrupt from Register 0. This bit is set when the Auto-Poll State Machine has detected
a change in the external PHY register whose address is stored in Auto-Poll Register 0.
19
MIIPDTINT
MII PHY Detect Transition Interrupt. The MII PHY Detect Transition Interrupt is set by the
Am79C976 controller whenever the MIIPD bit in STAT0 transitions from 0 to 1 or vice versa.
This bit is an alias of CSR7, bit 1.
18
MCCIINT
MII Management Command Complete Internal Interrupt. The MII Management Command
Complete Interrupt is set by the Am79C976 controller when a read or write operation on the MII
management port is complete from an internal operation. Examples of internal operations are Auto-
Poll or Network Port Manager generated MII management frames.
This bit is an alias of CSR7, bit 3.
17
MCCINT
MII Management Command Complete Interrupt. The MII Management Command Complete
Interrupt is set by the Am79C976 controller when a read or write operation to the MII Data Port
(PHY Access Register) is complete.
This bit is an alias of CSR7, bit 5.
相關(guān)PDF資料
PDF描述
AM79C976KIW PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
AM79C976KCW PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
AM79C978AKCW Single-Chip 1/10 Mbps PCI Home Networking Controller
AM79C978AVCW Single-Chip 1/10 Mbps PCI Home Networking Controller
AM79C978 Single-Chip 1/10 Mbps PCI Home Networking Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C976KC 制造商:Rochester Electronics LLC 功能描述:METRIC PLASTIC QUAD-RING - Bulk
AM79C976KCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
AM79C976KD 制造商:Advanced Micro Devices 功能描述:ETHERNET:MEDIA ACCESS CONTROLLER (MAC)
AM79C976KF 制造商:Advanced Micro Devices 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 208-Pin PQFP 制造商:AMD (Advanced Micro Devices) 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 208-Pin PQFP
AM79C976KI 制造商:Advanced Micro Devices 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 208-Pin PQFP 制造商:AMD (Advanced Micro Devices) 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 208-Pin PQFP
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*