
120
Am79C976
8/01/00
P R E L I M I N A R Y
3
PME_CLK
PME Clock. When this bit is a 1,
it indicates that the function relies
on the presence of the PCI clock
for PME operation. When this bit
is a 0 it indicates that no PCI
clock is required for the function
to generate PME.
Functions that do not support
PME generation in any state
must return 0 for this field.
Read only.
2-0
PMIS_VER Power Management Interface
Specification Version. A value of
010b indicates that this function
complies with the revision 1.1 of
the PCI Power Management In-
terface Specification.
008#!
:0#;
Offset 48h
Bit
Name
Description
15
PME_STATUS
PME Status. This bit is set when
the function would normally as-
sert the PME signal independent
of the state of the PME_EN bit.
Writing a 1 to this bit will clear it
and cause the function to stop as-
serting a PME (if enabled). Writ-
ing a 0 has no effect.
If the function supports PME from
D3cold then this bit is sticky and
must be explicitly cleared by the
operating system each time the
operating system is initially load-
ed.
Read/write accessible. Sticky bit.
This bit is reset by POR.
S_RESET or setting the STOP bit
has no effect. If the function does
not support PME# assertion from
D3cold, either because bit 15 of
the PMC Alias register is zero or
the VAUX_SENSE pin is low,
PME_STATUS will be reset fol-
lowing H_RESET. This reset is
actually done at the end of the
EEPROM read operation, since
bit 15 of the PMC Alias register
may be loaded from the EE-
PROM.
14-13
DATA_SCALE
Data Scale. This two bit read-
only field indicates the scaling
factor to be used when interpret-
ing the value of the Data register.
The value and meaning of this
field will vary depending on the
DATA_SCALE field.
Read only.
12-9
DATA_SEL Data Select. This optional four-bit
field is used to select which data
is reported through the Data reg-
ister and DATA_SCALE field.
Read/write accessible. Sticky bit.
This bit is reset by POR.
H_RESET, S_RESET, or setting
the STOP bit has no effect.
8
PME_EN
PME
PME_EN enables the function to
assert PME. When a 0, PME as-
sertion is disabled.
Enable.
When
a
1,
This bit defaults to
“
0
”
if the func-
tion does not support PME gener-
ation from D3cold.
If the function supports PME from
D3cold, then this bit is sticky and
must be explicitly cleared by the
operating system each time the
operating system is initially load-
ed.
Read/write accessible. Sticky bit.
This bit is reset by POR.
S_RESET or setting the STOP bit
has no effect. If the function does
not support PME assertion from
D3cold, either because bit 15 of
the PMC Alias register is zero or
the VAUX_SENSE pin is low,
PME_STATUS will be reset fol-
lowing H_RESET. This reset is
actually done at the end of the
EEPROM read operation, since
bit 15 of the PMC Alias register
may
be
loaded
EEPROM.
from
the
7-2
RES
Reserved locations. Read only.
1-0
PWR_STATE