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參數(shù)資料
| 型號： | AM79C850KC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SUPERNET-R 3 |
| 中文描述： | 1 CHANNEL(S), 100M bps, FDDI CONTROLLER, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 35/97頁 |
| 文件大?。?/td> | 358K |
| 代理商： | AM79C850KC |
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P R E L I M I N A R Y
AMD
35
SUPERNET 3
Addition of Scrambler/Descrambler Function to
Support Copper PMD
This is a description of the Stream-Cipher Scrambler
and Descrambler as implemented in the physical layer
controller block.
The Stream-Cipher Scrambler adds the output of a
random generator to the data stream. The purpose is to
spread the spectrum and reduce frequency peaks. As a
result, higher signal amplitudes can be transmitted over
copper that meet the requirements of the FCC and other
regulatory agencies.
The random generator is the polynomial 2
11
+ 2
9
. The
SUPERNET 3 implementation uses a 5-bit parallel
technique. The 5-bit output of the random generator is
exclusive-ORed with the input to produce scrambled
data for transmission.
The descrambler has a random generator which is
identical to the random generator in the scrambler. The
output of this generator is used to decipher the received
scrambled data using the same exclusive-OR function.
Since both random generators are identical, the output
of the receiver random generator is the original data
(data XOR Random
→
XOR Random = data).
This process is open loop in nature, i.e., the data has no
effect on the states of the random generators. There-
fore, the descrambler must incorporate synchronization
circuitry to preset its state to the same state as the
scrambler. Once both random generators start from the
same state, they will remain in synchronization.
The synchronization circuitry, CREG and HREG regis-
ters, are designed to take advantage of the scrambled
FDDI line states. During the line states (HLS, QLS, MLS
and ILS), CREG and HREG generate known patterns.
When the synchronization circuitry detects these pat-
terns, it generates a capture signal and the correspond-
ing output data pattern.
CAPTURE controls the random generator. When it is
false, the random generator operates open loop. When
it is true, the random generator is preset to the deduced
output data exclusive-ORed with the input scrambled
data. This is equal to the state of the scrambler’s
random generator.
FDDI Line States & Detected Signals
Line State
Data Bits
Detected Bits
HLS
00010000100
00111001110
QLS
00000000000
00000000000
MLS
00000000100
00000001110
ILS
11111111111
11111111111
CAPTURE is enabled by SAMPLE, which is enabled by
SCRM_RESYNC. SCRM_RESYNC is active when
PHY line state is not Active Line State, or Unknown Line
State. A false SCRM_RESYNC indicates that the
decoded data is correct. Therefore the random genera-
tor is synchronized and SAMPLE is set false. SAMPLE
is set true when SCRM_RESYNC is true except during
the following condition:
If two consecutive IDLE bytes and then non-idle bytes
are detected when SCRM_RESYNC is true, SAMPLE
goes false and stays false for 32 RSCLK cycles. After
that
the
state
of
SCRM_RESYNC.
SAMPLE
depends
on
Testability
The Test Access Port (TAP)
An IEEE 1149.1 boundary-scan architecture is provided
for board level testing and diagnostics. All pins are part
of the boundary-scan ring except Digital Transmitter/
Receiver pseudo-analog (PECL) pins. The TAP con-
sists of five pins, TCK, TMS, TDI, TDO and
TRST
.
These pins are dedicated connections and may not be
used for any other purpose. The boundary-scan
architecture includes a TAP controller, an instruction
register and instruction decode logic, and a test data
register array.
The functional description of the TAP that follows is not a
complete description of the IEEE boundary-scan
architecture. Additional information and a more detailed
functional description can be found in the standard
document (IEEE Std 1149.1–1990). The description
provided
here
covers
particular implementation.
the
specifics
of
this
TAP Controller
The TAP controller is a synchronous 16-state finite state
machine which is driven by the TCK and TMS pins. All
state transitions of the TAP controller occur at the rising
edge of TCK. The transitions are based on the value of
TMS at the rising edge of TCK. In the Test-Logic-Reset
state the instruction register is initialized with the
IDCODE instruction. The TAP controller is forced to the
Test-Logic-Reset state whenever a logic 0 is placed on
the
TRST
pin. A system reset has no effect on the
TAP controller.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C850KCW | SUPERNET-R 3 |
| AM79C864AKC | Physical Layer Controller With Scrambler (PLC-S) |
| AM79C864AKCW | Physical Layer Controller With Scrambler (PLC-S) |
| AM79C873 | NetPHY⑩ -1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support |
| AM79C873KCW | NetPHY⑩ -1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C850KCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:SUPERNET-R 3 |
| AM79C864A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Physical Layer Controller With Scrambler (PLC-S) |
| AM79C864AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Physical Layer Controller With Scrambler (PLC-S) |
| AM79C864AKCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Physical Layer Controller With Scrambler (PLC-S) |
| AM79C864KC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Transceiver |
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