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參數(shù)資料
| 型號： | AM79C850KC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SUPERNET-R 3 |
| 中文描述： | 1 CHANNEL(S), 100M bps, FDDI CONTROLLER, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 29/97頁 |
| 文件大?。?/td> | 358K |
| 代理商： | AM79C850KC |
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P R E L I M I N A R Y
AMD
29
SUPERNET 3
(if transmitting), releases the token, and no further
transmissions can occur until the pin is deasserted.
During the time that the TRANSMIT INHIBIT function is
enabled the network timers and state machines
operate normally.
As a result of the change to the FLXI pin, which of the
two functions is selected depends upon the state of FLXI
bits, as follows:
FLXI
Pin
FLXI1
FLXI0
Function Implemented
0
0
0
Normal Operation
1
0
0
Normal Operation
0
0
1
Normal Operation
1
0
1
FLUSH received frame
0
1
0
Normal Operation
1
1
0
INHIBIT transmission
0
1
1
Reserved
1
1
1
Reserved
Upon reset, the FLXI1:0 bits would read all zeros.
Single Frame Receive Mode
The Single Frame Receive Mode function has been
removed from the SUPERNET 3. All associated status,
modes and commands are deleted and replaced with
reserved. This causes the following changes:
1. Status Register 2 Upper:
The ‘Receive Frame’ (SRCVFRM) bit 10 and
‘Receive Frame Counter Overflow’ (SRFRCTOV) bit
9 are now reserved and return a value of zero when
read.
2. Command Register 2:
The ‘Enable Receive Single Frame’ command
(0x40) is no longer a valid command. This is now
reserved.
3. Mode Register 1:
The ‘Single-Frame Receive Mode’ bit [15] is no
longer valid. It is now a reserved bit and shall return a
value of zero when read.
Receive Queue Operation
SUPERNET 3 provides a new feature where the user
can configure the buffer memory for incoming valid
frame into two separate receive queues. The type of
frames that each queue would receive is selected in a
separate register, the Frame Selection Register
(FRSELREG). To enable two receive queues operation,
MENDRCV bit in Mode Register 3 (MDREG3) needs to
be set. If this bit is cleared, which is the case at the time
of reset, then SUPERNET 3 behaves like F+ (i.e only
one receive queue is supported, and SUPERNET 3
defaults to Receive Queue 1). If MDREG3 bit 11,
MENDRCV and both RECVX3:0 in Frame Selection
Register (FRSELREG) is programmed to be “0000”
then the SUPERNET 3 would behave like FORMAC+
and the second queue is ignored. However, if one of the
RECVX3:0 bits in FRSELREG are programmed to be
“0000” then the corresponding queue would receive all
frames except the frame type selected for the other
queue. Only the second receive queue (i.e. RECV2) can
be programmed to be “0000”. Programming the RECV1
bits in the Frame Selection Register (FRSELREG) with
“0000” and RECV2 bits with a non-zero selection, will
result in no data being written in the RECV1 queue. Only
the frame type selected by RECV2 bits will be received
in the second queue.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C850KCW | SUPERNET-R 3 |
| AM79C864AKC | Physical Layer Controller With Scrambler (PLC-S) |
| AM79C864AKCW | Physical Layer Controller With Scrambler (PLC-S) |
| AM79C873 | NetPHY⑩ -1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support |
| AM79C873KCW | NetPHY⑩ -1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C850KCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:SUPERNET-R 3 |
| AM79C864A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Physical Layer Controller With Scrambler (PLC-S) |
| AM79C864AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Physical Layer Controller With Scrambler (PLC-S) |
| AM79C864AKCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Physical Layer Controller With Scrambler (PLC-S) |
| AM79C864KC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Transceiver |
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