參數(shù)資料
型號(hào)： AM79C850KC
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： SUPERNET-R 3
中文描述： 1 CHANNEL(S), 100M bps, FDDI CONTROLLER, PQFP208
封裝： PLASTIC, QFP-208
文件頁數(shù)： 15/97頁
文件大?。?/td> 358K
代理商： AM79C850KC
P R E L I M I N A R Y
AMD
15
SUPERNET 3
word and the descriptor word at the end of the frame. In
transmit mode, when BDTAG = 0, it indicates that the
information on the BD bus is data, i.e., end-of-frame not
yet reached.
CSO
Chip-Select Output (TTL output, high impedance,
active low)
The chip-select output (active low) is a select signal for
buffer memory read and write operations. This line is in
the high-impedance state when buffer memory control
is released to the NP.
RD
Buffer Memory Read (TTL output, high
impedance, active low)
This output signal (active low) controls the buffer
memory during a buffer-memory read accesses. This
line is in the high-impedance state when buffer memory
control is released to the NP.
WR
Buffer Memory Write (TTL output, high
impedance, active low)
This (active low) output signal, in its active-low state,
allows write accesses to buffer memory. This line is in
the high-impedance state when buffer memory control
is released to the NP.
Host/Buffer Memory Interface (10 Pins)
All these signals are synchronous to BMCLK.
HSACK
Host Acknowledge (TTL output, high impedance)
This signal indicates that the current host read/write
request is being granted by SUPERNET 3 and allows
read/write accesses of buffer memory by the host.
HSREQ2–0
Host Request Bus (TTL input)
The host request bus specifies to SUPERNET 3 the type
of buffer memory access the host requires, as described
in the following table.
Special-frame write requests are used to set up claim,
beacon, and auto-void frames in the buffer memory (see
the discussion under Buffer Memory Operation in
SUPERNET 2 data book). These requests make use of
the WPXSF register to set up special frames in the
special-frame area.
Read request is used to retrieve received frames from
buffer memory and store them in the system memory.
Write requests are used to set up frames in buffer
memory for transmission.
HSREQ2
HSREQ1
HSREQ0
Type of Request
0
0
0
None.
0
0
1
Read Request:
Second Receive
Queue*
0
1
0
Special Frame
Write Request.
0
1
1
Read Request:
Receive Queue.
1
0
0
Write Request:
Synchronous Queue.
1
0
1
Write Request:
Asynchronous
Queue 0.
1
1
0
Write Request:
Asynchronous
Queue 1.
1
1
1
Write Request
Asynchronous
Queue 1.
Note:
* Only if two receive queue operation is selected
through MDREG3.
QCTRL2–0
Buffer Queue Control (TTL output, high
impedance)
The QCTRL2–0 status output lines are encoded as de-
scribed in the following table.
相關(guān)PDF資料
PDF描述
AM79C850KCW SUPERNET-R 3
AM79C864AKC Physical Layer Controller With Scrambler (PLC-S)
AM79C864AKCW Physical Layer Controller With Scrambler (PLC-S)
AM79C873 NetPHY⑩ -1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support
AM79C873KCW NetPHY⑩ -1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C850KCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:SUPERNET-R 3
AM79C864A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Physical Layer Controller With Scrambler (PLC-S)
AM79C864AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Physical Layer Controller With Scrambler (PLC-S)
AM79C864AKCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Physical Layer Controller With Scrambler (PLC-S)
AM79C864KC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Transceiver
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