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參數(shù)資料
| 型號： | AM79C30A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Digital Subscriber Controller⑩ (DSC⑩) Circuit |
| 中文描述： | 數(shù)字用戶控制器⑩法（DSC⑩）電路 |
| 文件頁數(shù)： | 9/101頁 |
| 文件大小： | 1607K |
| 代理商： | AM79C30A |
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Am79C30A/32A Data Sheet
9
The LIU receiver is enabled, detects an incoming
signal on the S/T Interface, and achieves activation
as indicated by a transition to state F7. Both the INT
pin and the F7 transition interrupt must be enabled
for Power-Down mode to be exited. If the LIU is en-
abled, it may restart the oscillator so that it can iden-
tify the activity on the interface. If the activity is
determined to be noise, the LIU will stop the oscilla-
tor and continue to monitor the line without an inter-
rupt or returning to Idle mode.
The IOM-2 Interface is enabled as a clock master
and the SBIN input pin goes Low. This indicates that
a slave device wants to activate the IOM-2 Interface
and communicate with the DSC circuit. Both the INT
pin and the IOM-2 timing request interrupts must be
enabled for Power-Down mode to be exited.
The IOM-2 Interface is enabled as a clock slave and
the SCLK input pin goes High. This indicates that
the master device is activating the IOM-2 Interface
and the DSC circuit must wake up in order to moni-
tor the data. Both the INT pin and the IOM-2 timing
request interrupts must be enabled for Power-Down
mode to be exited.
If the DSC/IDC circuit is awakened by any condition
other than RESET, the MCLK output will be restored to
its previously programmed frequency, and will not gen-
erate any shortened or spurious output cycles. If the
DSC/IDC circuit is revived by RESET, MCLK will default
to its normal 6.144-MHz rate. The DSC/IDC circuit pro-
vides a minimum of two MCLK cycles prior to activating
the interrupt pin when exiting Power-Down mode.
MCLK Frequency Control
The MCLK frequency selection bits in the INIT register
are unchanged from Revision D. However, additional
MCLK frequencies are available by programming bits in
the INIT2 register. No shortened or spurious clock
pulses that might disrupt the external microprocessor
will result when the MCLK frequency is changed.
In order to reduce the probability of errant software dis-
rupting system operation, the INIT2 register requires
two consecutive writes before the value will be entered
into the register. Note that there will be no MCLK count-
down as is the case for entering Power-Down mode if
INIT2 is programmed to cause MCLK to STOP, and
there will be no shortened or spurious MCLK pulses.
MCLK Clock Speed-up Function
A programmable automatic MCLK speed-up option is
provided that will force a hardware reset of INIT2 bits
3-0, which will cause the MCLK frequency to be re-
stored to the value programmed in the INIT register.
There are two events that will trigger the clock
speed-up function:
1. The DLC receive FIFO threshold has been reached;
or,
2. a second packet begins to be received while data
from a prior packet is still in the receive FIFO.
The second packet case requires provision of an inter-
rupt; see the DLC register section for further informa-
tion. The clock speed-up function allows the user to
program a very slow MCLK frequency using INIT2
when D-channel activity is minimal. If a burst of activity
is seen on the D channel and it exceeds the pro-
grammed threshold of the receive FIFO or threatens to
overrun the receive FIFO status buffers, MCLK will in-
stantly toggle back to the higher frequency pro-
grammed in the INIT register. This eliminates the
latency incurred if an interrupt has to be serviced to
change the clock speed, and allows the overall system
power to be reduced during typical voice connections.
Note that automatic clock speed-up will not function un-
less at least one of the associated interrupts are en-
abled so the processor can be informed that the clock
speed has been altered.
Global Register Functions
INIT Register (INIT) default = 00H
Address = Indirect 21 Hex, Read/Write
Table 1.
INIT Register
Bit
Function
7
6 5 4 3
2
1
0
X X
X
X
X
X
0
0 Idle mode
X X
X
X
X
X
0
1 Active Voice and Data mode
X X
X
X
X
X
1
0 Active Data Only mode
X X
X
X
X
X
1
1 Power-Down mode
X X
X
X
X
0
X
X INT output enabled
X X
X
X
X
1
X
X INT output disabled
X X
0
0
0
X
X
X MCLK frequency = 6.144 MHz
X X
0
0
1
X
X
X MCLK frequency = 12.288 MHz
X X
0
1
0
X
X
X MCLK frequency = 3,072 MHz
X X
0
1
1
X
X
X MCLK frequency = 6.144 MHz
X X
1
0
0
X
X
X MCLK frequency = 4.096 MHz
X X
1
0
1
X
X
X MCLK frequency = 6.144 MHz
X X
1
1
0
X
X
X MCLK frequency = 6.144 MHz
X X
1
1
1
X
X
X MCLK frequency = 6.144 MHz
X 0
X
X
X
X
X
X DLC receiver abort disabled
X 1
X
X
X
X
X
X DLC receiver abort enabled
0 X
X
X
X
X
X
X DLC transmitter abort disabled
1 X
X
X
X
X
X
X DLC transmitter abort enabled
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