參數(shù)資料
型號: AM79C30A
廠商: Advanced Micro Devices, Inc.
英文描述: Digital Subscriber Controller⑩ (DSC⑩) Circuit
中文描述: 數(shù)字用戶控制器⑩法(DSC⑩)電路
文件頁數(shù): 45/101頁
文件大?。?/td> 1607K
代理商: AM79C30A
Am79C30A/32A Data Sheet
45
D-Channel Status Register 1 — (DSR1) — Read Only
DSR1 has the format shown in Table 44.
The DSR1 bits generate interrupts and are set/reset under the conditions shown in Table 45 (in addition to a hard-
ware reset or Idle mode).
Table 45.
DSR1 Interrupts
Table 44.
D-Channel Status Register 1
Bit
Logical 1
Logical 0 (Default Value)
0
Valid Address (VA) if the address decode logic is enabled or
End-of-Address (EOA) if the address decode logic is disabled
No valid address
1
End of receive packet
Not end of packet
2
Packet reception in progress
Packet not being received
3
Loopback in operation at Am79C30A/32A
No loopback in operation at Am79C30A/32A
4
Loopback in operation at LIU
No loopback in operation at LIU
5
D-channel back-off not in operation
D-channel back-off in operation
6
End of valid transmit packet
No end-of-transmit packet or no transmission
7
Current transmit packet has been aborted
No transmit packet abort
Bit Generate Interrupt
Bit Set
Bit Reset
0
Yes, if DMR3 bit 0 = 1 Two bytes after an opening flag if a VA is
decoded or address recognition is disabled
When the microprocessor reads DSR1 or
associated DRCR
1
Yes, if DMR1 bit 3 = 1 When a closing flag is received
When the microprocessor reads DSR1 or
associated DRCR
2
No
One byte after the opening flag of any packet,
valid or not
When a flag or an abort is received
3
No
When the operation is in progress
When the operation is not in progress
4
No
When the operation is in progress
When the operation is not in progress
5
No
When the operation is in progress
When the operation is not in progress
6
Yes, if DMR3 bit 1 = 1 When the closing flag is transmitted
When the microprocessor reads DSR1 or when
DTCR is loaded
7
No
When seven 1s and a 0 have been transmitted When the microprocessor reads DSR1 or when
DTCR is loaded
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