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參數(shù)資料
| 型號(hào)： | AM79C30A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Digital Subscriber Controller⑩ (DSC⑩) Circuit |
| 中文描述： | 數(shù)字用戶控制器⑩法（DSC⑩）電路 |
| 文件頁(yè)數(shù)： | 32/101頁(yè) |
| 文件大?。?/td> | 1607K |
| 代理商： | AM79C30A |
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32
Am79C30A/32A Data Sheet
processor that the MAP digital circuitry is functional.
Note that the digital patterns received after loopback
will not be identical to the transmitted patterns. The
D-D gain is approximately 2.5 dB.
MAP Digital Loopback 2
This loopback mode connects the analog D/A output
path to the analog A/D input path, internal to the DSC
circuit. The EAR and LS outputs and both AIN inputs
will be disabled. This mode allows verification from the
S Interface or microprocessor that the MAP analog and
digital circuitry are functional. The digital patterns re-
ceived after loopback will not be identical to the trans-
mitted patterns.
The bits in the MAP mode Register define the en-
able/disable options for the various MAP configurations
as follows.
MAP Registers
The MAP contains the programmable registers found in
Table 31.
Note:
It is necessary to complete any transfers to the multi-byte
MAP registers. For instance, a total of 16 bytes must be trans-
ferred to update the X filter.
Following reset, the MAP registers FTGR, MMR1,
MMR2, MMR3, STRA, and STRF all default to 00 hex.
All other MAP registers are not affected by reset and
must be programmed by the microprocessor before
being enabled. When the registers are disabled, or
after reset, the MAP will have the response shown in
Table 32.
Table 31.
Map Registers
MAP Register
Bytes Mnemonic
X-filter Coefficient Register
16
X
R-filter Coefficient Register
16
R
GX-Gain Coefficient Register
2
GX
GR-Gain Coefficient Register
2
GR
GER-Gain Coefficient Register
2
GER
Sidetone-Gain Coefficient Register
2
STGR
Frequency Tone Generator Register
2
FTGR
Amplitude Tone Generator Register
2
ATGR
MAP mode Registers (3)
1
MMR
Secondary Tone Ringer Amplitude
Reg
1
STRA
Secondary Tone Ringer Frequency
Reg
1
STRF
Transmit Peak Register
1
PEAKX
Receive Peak Register
1
PEAKR
Table 32.
Default Values
Filter
Default Response
X filter
Disabled (0 dB, Flat)
R filter
Disabled (0 dB, Flat)
GX filter
Disabled (0 dB, Gain)
GR filter
Disabled (0 dB, Gain)
GER filter
Disabled (0 dB, Gain)
Sidetone gain
Disabled (–18 dB, Gain)
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相關(guān)代理商/技術(shù)參數(shù) |
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| AM79C30ADC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN Line Interface |
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| AM79C30AJC | 制造商:Advanced Micro Devices 功能描述: 制造商:AMD 功能描述: |
| AM79C30AJC/D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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