參數(shù)資料
型號(hào)： AM79C30A
廠商： Advanced Micro Devices, Inc.
英文描述： Digital Subscriber Controller⑩ (DSC⑩) Circuit
中文描述： 數(shù)字用戶(hù)控制器⑩法（DSC⑩）電路
文件頁(yè)數(shù)： 61/101頁(yè)
文件大小： 1607K
代理商： AM79C30A
Am79C30A/32A Data Sheet
61
Peripheral Port Control Register 1 (PPCR1) — (continued)
Peripheral Port Status Register (PPSR)
Default = Bit 1 = 1, Bits 6–2 and 0 = 0, Bit 7 is Indeterminate
Address = Indirect C1 Hex, Read
The Peripheral Port Status Register presents various status conditions to the user, and is only used in the IOM-2
mode. Each of these conditions can generate an interrupt to the user. The interrupts are enabled via the Peripheral
Port Interrupt Enable Register. The state of the respective interrupt enable bits does not affect the setting of bits in
this register. Bits 6, 3, and 2 are cleared when this register is read. Bit 1 is cleared when the Data Register is written,
and bit 0 is cleared when the Data Register is read. In addition, bits 3, 2, 1, and 0 are cleared when the Monitor
channel is disabled (via bit 6 of the PPCR1 Register). Because bit 7 is reserved, the default value of this register is
either 02H or 82H.
Bit
1–0
Function
Port Mode Select Field—
These two bits select the configuration of the Peripheral Port as follows.
Bit
Function
1
0
0
0
Port Disabled
0
1
SBP mode enabled
1
0
IOM-2 Slave mode enabled
1
1
IOM-2 Master mode enabled
When the port is disabled, SBOUT, SBIN, and all port-related clocks are placed in a high-impedance state.
When the DSC circuit is reset, this bit field is set to 01, and the port is not enabled until a MUX MCR register is written
to. If this bit is cleared prior to such a path being programmed, the port will remain disabled until the bit is set via a
software write operation.
7
6
5
4
3
2
1
0
RSRVD
IOM-2
TIME
RQST
CHNG
IN
C/I 1
DATA
CHNG
IN
C/I 0
DATA
MONTR
ABORT
RECVD
MONTR
EOM
RECVD
MONTR
XMIT
BUFFR
AVAIL
MONTR
RECV
DATA
AVAIL
Bit
6
Function
IOM-2 Timing Request—
When the DSC circuit is the upstream device (master mode), this bit is set by hardware to
indicate that a downstream device has requested the starting of the IOM-2 clocks. The clocks are started by software.
This bit does not indicate the receipt of an activation request on the C/I channel. When the DSC circuit is the downstream
component (slave mode), this bit is set in response to SCLK starting (going High) when the bus is deactivated.
Notes:
1. The DSC circuit will not exit Power-Down mode in response to either a timing request or the clocks being started if
this interrupt is masked. It is essential that an interrupt be generated when the DSC circuit leaves Power-Down mode.
Otherwise, power consumption could increase significantly without the processor’s knowledge.
Change in C/I 1 Channel Status—
This bit is set by hardware to indicate that the contents on the receive side of C/I
channel 1 have changed since the C/I Receive Data Register was last read.
Change in C/I 0 Channel Status—
This bit is set by hardware to indicate that the contents on the receive side of C/I
channel 0have changed since the C/I Receive Data Register was last read.
Monitor Channel Abort Request Received—
This bit is set by hardware to indicate that an abort request has been
received on the monitor channel. This indicates that the receiver on the other end of the Monitor channel has failed to
receive the transmitted data correctly and requests that the current transmission be discontinued and the data
transmission repeated via software.
Monitor Channel End-of-Message Indication Received—
This bit is set by hardware to indicate that an abort request
has been received on the monitor channel. This indicates that the message currently being received has concluded.
Monitor Channel Transmit Buffer Available—
This bit is set by hardware to indicate that a new byte of data can be
loaded into the Monitor Transmit Data Register.
Monitor Channel Receive Data Available—
This bit is set by hardware to indicate that a byte of data has been received
on the monitor channel and is available in the Monitor Receive Data Register.
5
4
3
2
1
0
相關(guān)PDF資料
PDF描述
AM79C30AJC Digital Subscriber Controller⑩ (DSC⑩) Circuit
AM79C30AVC Digital Subscriber Controller⑩ (DSC⑩) Circuit
AM79C32A Digital Subscriber Controller⑩ (DSC⑩) Circuit
AM79C32AJC Digital Subscriber Controller⑩ (DSC⑩) Circuit
AM79C32AVC Digital Subscriber Controller⑩ (DSC⑩) Circuit
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C30ADC 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:ISDN Line Interface
AM79C30ADCB 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:ISDN Line Interface
AM79C30AJC 制造商:Advanced Micro Devices 功能描述: 制造商:AMD 功能描述:
AM79C30AJC/D 制造商:Rochester Electronics LLC 功能描述:- Bulk
AM79C30AJC/DTR 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*