參數(shù)資料
型號： AM79C30A
廠商： Advanced Micro Devices, Inc.
英文描述： Digital Subscriber Controller⑩ (DSC⑩) Circuit
中文描述： 數(shù)字用戶控制器⑩法（DSC⑩）電路
文件頁數(shù)： 12/101頁
文件大?。?/td> 1607K
代理商： AM79C30A
12
Am79C30A/32A Data Sheet
Table 4.
Format of the Interrupt Register (IR), Read Only
Bit
0
1
2
Interrupt Generated/Action Required
D-channel transmit threshold interrupt/load D-channel Transmit buffer
D-channel receive threshold interrupt/read D-channel Receive buffer
D-channel status interrupt/read DSR1
Source
Cause
DSR1 bit 0
Valid Address (VA) or End of Address (EOA)
DSR1 bit 1
When a closing flag is received or a receive error occurs
DSR1 bit 6
When a closing flag is transmitted DMR3 bit 1
D-channel error interrupt/read DER and DSR2 bit 2
Source
Cause
DER bit 0
Current received packet has been aborted
DER bit 1
Non-integer number of bytes received
DER bit 2
Collision abort detected
DER bit 3
FCS error
DER bit 4
Overflow error
DER bit 5
Underflow error
DER bit 6
Overrun error
DER bit 7
Underrun error
DSR2 bit 2
Receive packet lost
Bb or Bc byte available or buffer empty interrupt/read or write Bb or Bc buffers
LIU status interrupt/read LSR
Source
Cause
LSR bit 3
Change of state to F3
LSR bit 4
Change of state from/to F7
LSR bit 5
Change of state from/to F8
LSR bit 7
HSW change of state
D-channel status interrupt/read DSR2
Source
Cause
DSR2 bit 0
Last byte of received packet
DSR2 bit 1
Receive byte available
DSR2 bit 3
Last byte transmitted
DSR2 bit 4
Transmit buffer available
DSR2 bit 7
Start of second packet
Multiframe or PP interrupt/read MFSB and PPSR
Source
Cause
MFSB bit 5
S-data available
MFSB bit 6
Q-bit buffer empty
MFSB bit 7
Multiframe change of state (in/out of sync)
PPSR bit 0
Monitor receive, data available
PPSR bit 1
Monitor transmit, buffer available
PPSR bit 2
Monitor EOM received
PPSR bit 3
Monitor abort received
PPSR bit 4
C/I channel 0, data change
PPSR bit 5
C/I channel 1, data change
PPSR bit 6
IOM-2 timing request
Interrupt Mask
DMR1 bit 0
DMR1 bit 1
DMR3 bit 0
DMR1 bit 3
DMR3 bit 1
3
DMR2 bit 0
DMR2 bit 1
DMR2 bit 2
DMR2 bit 3
DMR2 bit 4
DMR2 bit 5
DMR2 bit 6
DMR2 bit 7
DMR3 bit 6
MCR4 bit 3
4
5
LMR2 bit 3
LMR2 bit 6
LMR2 bit 4
LMR2 bit 5
6
DMR3 bit 2
DMR3 bit 3
DMR3 bit 4
DMR3 bit 5
EFCR bit 1
7
MF bit 1
MF bit 2
MF bit 3
PPIER bit 0
PPIER bit 1
PPIER bit 2
PPIER bit 3
PPIER bit 4
PPIER bit 5
PPIER bit 6
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