- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366548 > Am7969 (Advanced Micro Devices, Inc.) TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) PDF資料下載
參數(shù)資料
| 型號： | Am7969 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| 中文描述： | TAXIchip集成電路（透明異步Xmitter，接收器接口） |
| 文件頁數(shù)： | 85/127頁 |
| 文件大小： | 730K |
| 代理商： | AM7969 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁當前第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁
AMD
81
TAXIchip Integrated Circuits Technical Manual
T he Data Out Lines
When a Receiver sees the Sync symbol it sends the data byte it just received from its
Input Latch to its Decoder Latch, and then the receiver lowers its IGM. One more clock
cycle is required for the data to go to the Output Latch. At this point DSTRB is raised. In
this way all data bytes are output simultaneously from all receivers, two clock cycles
after the first Sync (or two clock cycles after a LOW CNB). The DSTRBs of all the
receivers rise simultaneously as well.
T he V LT N (V iolation) Pin
In Cascade mode the VLTN pin acts exactly like a Data Out line. The timings are exactly
the same. Violations do not change the output of the IGM pin. i.e., a Receiver that gets a
VLTN will still raise it’s IGM signal as if it received a valid data byte.
7.3 Auto-Repeat Configuration
7.3.1 Rec eiver Connec tions in Auto-Repeat Configuration
In Auto-repeat Configuration the IGM of the last Receiver on the line is inverted and tied
to the CNB of the Primary Receiver. This connection eliminates the need to send a Sync
between each Data Word.
In a 3-Receiver cascade system, IGM3 is inverted and tied to CNB1. When the IGM of
the last Receiver goes high, CNB1 goes LOW.
CNB1 going LOW ripples through the chain pulling each IGM LOW (t46 ns) until finally
the last IGM goes LOW again, pulling CNB1 HIGH resetting RX1 to receive new data.
In Figures 7-6 and 7-7, as each Receiver decodes its data byte, it raises its IGM and
thus the next Receiver’s CNB.
Figure 7-6
T AX I Rec eiver—Casc aded in Auto-Repeat
SERIN+
SERIN–
CNB
IGM
DSTRB
CSTRB
CNB
IGM
DSTRB
CSTRB
CNB
IGM
DSTRB
CSTRB
CNB
IGM
DSTRB
CSTRB
12330E-28
相關PDF資料 |
PDF描述 |
|---|---|
| Am7968-125DKC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| Am7969-125DKC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| Am7968-175DKC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| Am7969-175DKC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| Am7969-125 | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM7969-100/B3A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver |
| AM7969-100/BXA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver |
| AM7969-100DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver |
| AM7969-100DCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver |
| AM7969-100DE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver |
發(fā)布緊急采購，3分鐘左右您將得到回復。