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參數(shù)資料
| 型號(hào)： | Am7969 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| 中文描述： | TAXIchip集成電路（透明異步Xmitter，接收器接口） |
| 文件頁(yè)數(shù)： | 63/127頁(yè) |
| 文件大?。?/td> | 730K |
| 代理商： | AM7969 |
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AMD
59
TAXIchip Integrated Circuits Technical Manual
4.0 CLOCK GENERAT ION AND DIS T RIBUT ION
The serial baud rate for the Am7968 Transmitter is derived from a byte rate frequency
source. The TAXI Receiver must run at the same frequency as the TAXI Transmitter.
The relationship between serial baud rate and data byte rate depends on the width of
the transmitted data. For 8-bit data, the byte rate is multiplied by 10 to obtain the serial
clock rate. Since the maximum operating frequency is 125 MHz and the minimum
frequency is 40 MHz, the byte rate frequency range for 8-bit data is between 4.0 and
12.5 MHz. The multipliers for 9 and 10 bit data widths are 11 and 12 respectively. The
following table summarizes the byte rate frequency ranges for each data width selected.
Am7968/Am7969-125
Data Width
PLL Multiplier
Byte Rate
8
9
10
11
2
4.00 – 12.50 MHz
3.64 – 11.36 MHz
3.33 – 10.42 MHz
10
Am7968/Am7969-175
Data Width
PLL Multiplier
Byte Rate
8
9
10
11
12
12.5 –17.5 MHz
11.37 – 15.90 MHz
10.42 – 14.58 MHz
10
The source of byte rate frequency can be either from the built-in crystal oscillator or from
a TTL clock signal. The maximum allowable mismatch between Transmitter and
Receiver frequency sources is
±
0.1%. This tolerance is derived from the PLL architec-
ture in the TAXI Receiver, and from considerations of crystal accuracy. More information
on crystal specifications and available distributors can be found in Appendix C, TAXI TIP
#89-05, TAXIchip set crystal specification.
When there is no incoming data, the Receiver PLL has no serial data stream to track.
This situation can arise if the Transmitter has not been powered up, or if the transmis-
sion medium is disconnected. In this case the VCO will drift to a frequency determined
by internal component tolerances. When data appears at the Receiver serial input, the
loop must acquire lock from this resting frequency. The worst case frequency offset and
the capture range of the PLL are designed to allow frequency mis-matching between
Transmitter and Receiver of
±
0.1%, since this accuracy is achievable with inexpensive
available crystals.
4.1 T AX I T ransmitter Cloc k Connec tions
The byte rate frequency source drives a multiplying PLL to create an internal bit rate
clock which is used for timing all internal logic. The X1 and X2 pins are used to input the
byte rate frequency source to the Transmitter. Their exact usage will vary, depending on
type of frequency source (crystal or external TTL) and mode of TAXI Transmitter
operation (Local or Test).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Am7968-125DKC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| Am7969-125DKC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| Am7968-175DKC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| Am7969-175DKC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| Am7969-125 | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM7969-100/B3A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver |
| AM7969-100/BXA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver |
| AM7969-100DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver |
| AM7969-100DCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver |
| AM7969-100DE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver |
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