參數(shù)資料
型號： Am7969
廠商： Advanced Micro Devices, Inc.
英文描述： TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface)
中文描述： TAXIchip集成電路（透明異步Xmitter，接收器接口）
文件頁數(shù)： 83/127頁
文件大小： 730K
代理商： AM7969
AMD
79
TAXIchip Integrated Circuits Technical Manual
Figure 7-4
Rec eiver T iming—8-Bit Casc ade Mode
Internal
Clock*
SERIN
Serial Data
NRZ Data*
CLK OUT
IGM TAXI #1 =
CNB TAXI #2
DATA OUT
Command
OUT
DSTRB OUT
Command
OUT
DATA OUT
DATA N
DATA N
SYNC
DATA 1
DATA 2
SYNC
SYNC
SYNC
3
2
NO CHANGE
COMMAND 0
1 1 0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 0 0 1
NO CHANGE
NO CHANGE
NO CHANGE
NO CHANGE
CNB TAXI #1 = 1
NO CHANGE
NO CHANGE
NO CHANGE
NO CHANGE
DATA N–1
NO CHANGE
NO CHANGE
NO CHANGE
NO CHANGE
DATA N
NO CHANGE
1
4
5
6
1 1 0 0 0 1 0 0 0 1
SYNC
DATA 1
DATA 2
1 1 0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 0 0 1
CSTRB OUT
NO CHANGE
NO CHANGE
NO CHANGE
NO CHANGE
NO CHANGE
CSTRB OUT
DSTRB OUT
* Internal Signals
1 1 0 0 0 1 0 0 0 1
SYNC
NO CHANGE
NO CHANGE
TAXI
#2
TAXI
#1
12330E-26
If CNB is HIGH, the Receiver will catch the next valid byte of data and hold it. It will not
attempt to catch any more data until it sees a Sync command from the Transmitter or
until its CNB goes LOW and then HIGH again.
If CNB is held LOW, the Receiver will not attempt to capture any data.
When the Primary Receiver RX1 catches a valid data byte it will raise its IGM (I Got
Mine) so the next Receiver RX2 can catch the next byte and so on down the line. After
all the receivers in the system have received their bytes a Sync must be sent or the next
byte of data will be lost
(3)
.
Referring to Figure 7-5 for a system of Cascaded Receivers.
(3)
In the Auto-Repeat Configuration, a Sync is not required.
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相關代理商/技術參數(shù)
參數(shù)描述
AM7969-100/B3A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver
AM7969-100/BXA 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver
AM7969-100DC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver
AM7969-100DCB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver
AM7969-100DE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver
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