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參數(shù)資料
| 型號： | Am7968-175LKC |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| 中文描述： | TAXIchip集成電路（透明異步Xmitter，接收器接口） |
| 文件頁數(shù)： | 82/127頁 |
| 文件大?。?/td> | 730K |
| 代理商： | AM7968-175LKC |
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AMD
78
TAXIchip Integrated Circuits Technical Manual
X1 is connected to a common Crystal Oscillator or a TTL Clock Source. It is not
recommended that X1 be connected to another Receiver’s CLK output.
X2 is grounded.
The DMS pins of all TAXls must be tied in the same state as the DMS pins on the
Transmitters.
The CSTRB/DSTRB pins on each of the Receivers are all active simultaneously. A
timing description for CSTRB and DSTRB is included in Appendix C, TAXI TIP #89-10
TAXI receiver CSTRB and DSTRB pulse width.
The VLTN pin has timing that is identical to the timing of the Data Out and the Com-
mand Out lines. Its connections are specific to each user’s applications.
If CNB is HIGH, the Receiver will catch the next valid byte of data and hold it. It will not
attempt to catch any more data until it sees a Sync command from the Transmitter or
until its CNB goes LOW and then HIGH again.
Figure 7-3
Rec eivers in Casc ade Mode
CSTRB CMD DATA DSTRB VLTN
CNB
DMS
CLK
X2
X1
IGM
V
CC
SERIN+
SERIN–
SERIN+
SERIN–
CSTRB CMD DATA DSTRB VLTN
CNB
DMS
X2
X1
IGM
CSTRB CMD DATA DSTRB VLTN
CNB
DMS
X2
X1
IGM
N/C
SERIN–
SERIN+
RX1
Am7969
PRIMARY RX
RX2
Am7969
RX3
Am7969
12.5 MHz
Crystal
OSC
D23-D16
D15-D8
D7-D0
*Transmission line terminations not shown.
12330E-25
The following section describes the functionality of individual pins:
T he DS T RB Pin
Any one of the DSTRBs may be used as the user’s DSTRB to his system. When an
entire word has been received (signified internally by a Sync from the Transmitter) the
data in the Receivers are latched out to the output ports and all the DSTRBs are raised
(simultaneously) one cycle later. Likewise, if Commands are sent as part of the cascade
word, the CSTRB/DSTRB connections must be made appropriately.
Timing description for receivers in cascade mode is included in Figure 7-4.
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PDF描述 |
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| Am7969-175LKC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7968-125VB3A | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7969-125VB3A | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7968-175JC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7969-175JC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM7968-175LMC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7968-175PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Transmitter |
| AM7968-175PCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Transmitter |
| AM7968-70/B3A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Transmitter |
| AM7968-70/BXA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Transmitter |
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