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參數(shù)資料
| 型號： | AM5X86 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能單片32位微處理器) |
| 中文描述： | 高性能設(shè)計(jì)的片上集成完整的32位架構(gòu)Micrprocessor（高性能單片32位微處理器） |
| 文件頁數(shù)： | 59/67頁 |
| 文件大?。?/td> | 1201K |
| 代理商： | AM5X86 |
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Am5
X
86 Microprocessor
59
AMD
PRELIMINARY
The AC specifications, provided in the AC characteris-
tics table, consist of output delays, input setup require-
ments, and input hold requirements. All AC specifica-
tions are relative to the rising edge of the CLK signal.
AC specifications measurement is defined by Figure 39.
All timings are referenced to 1.5 V unless otherwise
specified. Am5
X
86 microprocessor output delays are
33-MHz bus (133-MHz operating frequency)
V
CC
= 3.3 V ±0.3 V; T
CASE
= 0°C to + 85°C; C
L
= 50 pF unless otherwise specified
specified with minimum and maximum limits, measured
as shown. The minimum microprocessor delay times
are hold times provided to external circuitry. Input setup
and hold times are specified as minimums, defining the
smallest acceptable sampling window. Within the sam-
pling window, a synchronous input signal must be stable
for correct microprocessor operation.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
Preliminary Info
Min
8
30
Symbol
Parameter
Max
33
125
Unit
MHz
ns
Figure
Notes
Frequency
CLK Period
Note 2
t
1
39
t
1a
CLK Period Stability
0.1%
Adjacent Clocks
Notes 3 and 4
Note 3
Note 3
Note 3
Note 3
Note 5
t
2
t
3
t
4
t
5
CLK High Time at 2 V
CLK Low Time at 0.8 V
CLK Fall Time (2 V–0.8 V)
CLK Rise Time (0.8 V–2 V)
A31–A2, PWT, PCD, BE3–BE0, M/IO, D/C, CACHE,
W/R, ADS, LOCK, FERR, BREQ, HLDA,
SMIACT, HITM Valid Delay
A31–A2, PWT, PCD, BE3–BE0, M/IO, D/C, CACHE,
W/R, ADS, LOCK Float Delay
PCHK Valid Delay
BLAST, PLOCK, Valid Delay
BLAST, PLOCK, Float Delay
D31–D0, DP3–DP0 Write Data Valid Delay
D31–D0, DP3–DP0 Write Data Float Delay
EADS, INV, WB/WT Setup Time
EADS, INV, WB/WT Hold Time
KEN, BS16, BS8 Setup Time
KEN, BS16, BS8 Hold Time
RDY, BRDY Setup Time
RDY, BRDY Hold Time
HOLD, AHOLD Setup Time
BOFF Setup Time
HOLD, AHOLD, BOFF Hold Time
RESET, FLUSH, A20M, NMI, INTR, IGNNE,
STPCLK, SRESET, SMI Setup Time
RESET, FLUSH, A20M, NMI, INTR, IGNNE,
STPCLK, SRESET, SMI Hold Time
D31–D0, DP3–DP0, A31–A4 Read Setup Time
D32–D0, DP3–DP0, A31–A4 Read Hold Time
11
11
ns
ns
ns
ns
39
39
39
39
3
3
t
6
3
14
ns
40
t
7
3
20
ns
41
Note 3
t
8
t
8a
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
18a
t
19
3
3
3
3
3
5
3
5
3
5
3
6
7
3
14
14
20
14
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
42
40
41
40
41
43
43
43
43
44
44
43
43
43
Note 3
Note 3
t
20
5
ns
43
Note 5
t
21
3
ns
43
Note 5
t
22
t
23
5
3
ns
ns
43, 44
43, 44
Notes:
1. Specifications assume C
= 50 pF. I/O Buffer model must be used to determine delays due to loading (trace and component). First
Order I/O buffer models for the processor are available.
2. 0-MHz operation guaranteed during stop clock operation.
3. Not 100% tested. Guaranteed by design characterization.
4. For faster transitions (>0.1% between adjacent clocks), use the Stop Clock protocol to switch operating frequency.
5. All timings are referenced at 1.5 V (as illustrated in the listed figures) unless otherwise noted.
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