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參數(shù)資料
| 型號： | AM5X86 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能單片32位微處理器) |
| 中文描述： | 高性能設(shè)計的片上集成完整的32位架構(gòu)Micrprocessor（高性能單片32位微處理器） |
| 文件頁數(shù)： | 43/67頁 |
| 文件大?。?/td> | 1201K |
| 代理商： | AM5X86 |
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Am5
X
86 Microprocessor
43
AMD
PRELIMINARY
7.3.4
When SMI is recognized on an instruction boundary, the
CPU core first sets the SMIACT signal Low, indicating
to the system logic that accesses are now being made
to the system-defined SMRAM areas. The CPU then
writes its state to the state save area in the SMRAM.
The state save area starts at SMBASE + [8000h +
7FFFh]. The default CS Base is 30000h; therefore, the
default state save area is at 3FFFFh. In this case, the
CS Base is also referred to as the SMBASE.
SMRAM State Save Map
Table 10. SMRAM State Save Map
Register
Offset*
7FFCh
7FF8h
7FF4h
7FF0h
7FECh
7FE8h
7FE4h
7FE0h
7FDCh
7FD8h
7FD4h
7FD0h
7FCCh
7FC8h
7FC4h
7FC0h
7FBCh
7FB8h
7FB4h
7FB0h
7FACh
7FA8h
7FA7h–7F98h Reserved
7F94h
7F93h–7F8Ch Reserved
7F88h
7F87h–7F08h Reserved
7F04h
7F02h
7F00h
7EFCh
7EF8h
7EF7h–7E00h Reserved
Register
Writable
CRO
CR3
EFLAGS
EIP
EDI
ESI
EBP
ESP
EBX
EDX
ECX
EAX
DR6
DR7
TR*
LDTR*
GS*
FS*
DS*
SS*
CS*
ES*
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
No
IDT Base
GDT Base
I/O Trap Word
Halt Auto Restart
I/O Trap Restart
SMM Revision Identifier
State Dump Base
Note:
*Upper 2 bytes are not modified.
If the SMBASE relocation feature is enabled, the SM-
RAM addresses can change. The following formula is
used to determine the relocated addresses where the
context is saved: SMBASE + [8000h + Register Offset],
where the default initial SMBASE is 30000h and the
Register Offset is listed in Table 10. Reserved spaces
are for new registers in future CPUs. Some registers in
the SMRAM state save area may be read and changed
by the SMI handler, with the changed values restored
to the processor register by the RSM instruction. Some
register images are read-only, and must not be modified.
(Modifying these registers results in unpredictable be-
havior.) The values stored in the “reserved” areas may
change in future CPUs. An SMI handler should not rely
on values stored in a reserved area.
The following registers are written out during SMSAVE
mode to the RESERVED memory locations (7FA7h–
7F98h, 7F93h–7F8Ch, and 7F87h–7F08h), but are not
visible to the system software programmer:
I
DR3–DR0
I
CR2
I
CS, DS, ES, FS, GS, and SS hidden descriptor
registers
I
EIP_Previous
I
GDT Attributes and Limits
I
IDT Attributes and Limits
I
LDT Attributes, Base, and Limits
I
TSS Attributes, Base, and Limits
If an SMI request is issued to power down the CPU, the
values of all reserved locations in the SMM state save
area must be saved to non-volatile memory.
The following registers are not automatically saved and
restored by SMI and RSM:
I
TR7–TR3
I
FPU registers:
— STn
— FCS
— FSW
— Tag Word
— FP instruction pointer
— FP opcode
— Operand pointer
Note:
You can save the FPU state by using an FSAVE
or FNSAVE instruction.
For all SMI requests except for power down suspend/
resume, these registers do not have to be saved be-
cause their contents will not change. During a power
down suspend/resume, however, a resume reset clears
these registers back to their default values. In this case,
the suspend SMI handler should read these registers
directly to save them and restore them during the power
up resume. Anytime the SMI handler changes these
registers in the CPU, it must also save and restore them.
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