參數(shù)資料
型號(hào)： AM5X86
廠商： Advanced Micro Devices, Inc.
英文描述： High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能單片32位微處理器)
中文描述： 高性能設(shè)計(jì)的片上集成完整的32位架構(gòu)Micrprocessor（高性能單片32位微處理器）
文件頁(yè)數(shù)： 55/67頁(yè)
文件大?。?/td> 1201K
代理商： AM5X86
Am5
X
86 Microprocessor
55
AMD
PRELIMINARY
I
Control (bits 1–0):
Read/Write, independent of Write-
through or Write-back mode. The control bits deter-
mine which operation to perform. The following is a
definition of the control operations:
— 00 = Write to cache fill buffer, or read from cache
read buffer
— 01 = Perform cache write
— 10 = Perform cache read
— 11 = Flush the cache (mark all entries invalid)
8.3
The following paragraphs provide examples of testing
the cache using TR4 and TR5.
Using TR4 and TR5 for Cache Testing
8.3.1
Example 1: Reading The Cache (Write-back
Mode Only)
Disable caching by setting the CD bit in the CR0
register.
In TR5, load 0 into the Ext field (bit 19), the required
index into the Index field (bits 10–4), the required
entry value into the Entry field (bits 3–2), and 10 into
the Control field (bits 1–0). Loading the values into
TR5 triggers the cache read. The cache read loads
the TR4 register with the TAG for the read entry,
and the LRU and Valid bits for the entire set that
was read. The cache read loads 128 data bits into
the cache read buffer. The entire buffer can be read
by placing each of the four binary combinations in
the Entry field and setting the Control field in TR5
to 00 (binary). Read each doubleword from the
cache read buffer through TR3.
Reading the Set State fields in TR4 during Write-
back mode is accomplished by setting the Ext field
in TR5 to 1 and rereading TR4.
8.3.2
Example 2: Writing The Cache
1)
Disable the cache by setting the CD bit in the CR0
register.
2.
In TR5, load 0 into the Ext field (bit 19), the required
entry value into the Entry field (bits 3–2), and 00 into
the Control field (bits 1–0).
3.
Load the TR3 register with the data to write to the
cache fill buffer. The cache fill buffer write is trig-
gered by loading TR3.
4.
Repeat steps 2 and 3 for the remaining three dou-
blewords in the cache fill buffer.
5.
In TR4, load the required values into TAG field (bits
31–11) and the Valid field (bit 10). In Write-back
mode, the Valid bit is ignored since the Set State
field in TR5 is used in place of the TR4 Valid bit. The
other bits in TR4 (9:0) have no effect on the cache
write.
1.
2.
3.
6.
In TR5, load 0 into the Ext field (bit 19), the required
value into the Set State field (bits 18–17) (Write-
back mode only), the required index into the Index
field (bits 10–4), the required entry value into the
Entry field (bits 3–2), and 01 into the Control field
(bits 1–0). Loading the values into TR5 triggers the
cache write. In Write-through mode, the Set State
field is ignored, and the Valid bit (bit 10) in TR4 is
used instead to define the state of the specified set.
8.3.3
Example 3: Flushing The Cache
The cache flush mechanism functions in the same way
in Write-back and Write-through modes. Load 11 into
the Control field (bits 1–0) of TR5. All other fields are
ignored, except for Ext in Write-back mode. The cache
flush is triggered by loading the value into TR5. All of
the LRU bits, Valid bits, and Set State bits are cleared.
9
Am5
X
86 CPU Functional Differences
Several important differences exist between Am5
X
86
microprocessors and standard Am486DX microproces-
sors:
I
The ID register contains a different version signa-
ture.
I
The EADS function performs cache line write-backs
of modified lines to memory in Write-back mode.
I
A burst write feature is available for copy-backs. The
FLUSH pin and WBINVD instruction copy back all
modified data to external memory prior to issuing the
special bus cycle or reset.
The Am5
X
86 processor is functionally identical to the
Enhanced Am486 processor except for the function of
the CLKMUL pin (see Section 9.3) and the redefinition
of TR4 and TR5 to access the 16-Kbyte cache (see
Section 8).
9.1
The RESET state is invoked either after power up or
after the RESET signal is applied according to the stan-
dard Am486DX microprocessor specification.
Status after Reset
9.2
After reset, the STATUS bits of all lines are set to 0. The
LRU bits of each set are placed in a starting state.
Cache Status
9.3
For the standard Am486 processor, the Enhanced
Am486 processor, and the Am5
X
86 processor, if the
CLKMUL pin is driven High at RESET, the processor
uses a Clock-tripled mode.
CLKMUL Pin
To ensure correct operation of the 133-MHz Am5
X
86
processor, always connect the CLKMUL input to V
SS
.
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