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參數(shù)資料
| 型號(hào)： | AM5X86 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能單片32位微處理器) |
| 中文描述： | 高性能設(shè)計(jì)的片上集成完整的32位架構(gòu)Micrprocessor（高性能單片32位微處理器） |
| 文件頁(yè)數(shù)： | 30/67頁(yè) |
| 文件大?。?/td> | 1201K |
| 代理商： | AM5X86 |
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30
Am5
X
86 Microprocessor
AMD
PRELIMINARY
Step 7 One clock cycle later BOFF is deasserted. The
write-back access starts one clock cycle later
because the BOFF has cleared the bus pipe-
line.
Step 8 AHOLD is deasserted. In the next clock cycle
the address for the write-back is driven on the
address bus.
Step 9 One cycle after BOFF is deasserted, the cache
immediately starts writing back the modified
line. This is indicated by ADS = 0 and W/R = 1.
Step 10The write-back access is finished when BLAST
and BRDY go active 0.
Step 11The BIU restarts the aborted cache line fill with
the previous read. This is indicated by ADS = 0
and W/R = 0.
Step 12In the same clock cycle, the snooping cache
drives HITM back to 1.
Step 13The previous read is now reread.
4.8.7
In addition to the previously described scenarios, there
are special scenarios regarding the time of the EADS
and AHOLD assertion. The final result depends on the
time EADS and AHOLD are asserted relative to other
processor-initiated operations.
Special Scenarios for AHOLD Snooping
4.8.7.1
Scenario
: The MESI cache protocol and the ability to
perform and respond to snoop cycles guarantee that
writes to the cache are logically equivalent to writes to
memory. In particular, the order of read and write oper-
ations on cached data is the same as if the operations
were on data in memory. Even non-cached memory
read and write requests usually occur on the external
bus in the same order that they were issued in the pro-
gram. For example, when a write miss is followed by a
read miss, the write data goes on the bus before the
read request is put on the bus. However, the posting of
writes in write buffers coupled with snooping cycles may
cause the order of writes seen on the external bus to
differ from the order they appear in the program. Con-
sider the following example, which is illustrated in Figure
14. For simplicity, snooping signals that behave in their
usual manner are not shown.
Write Cycle Reordering due to Buffering
Step 1 AHOLD is asserted. No further processor-initi-
ated accesses to the external bus can be start-
ed. No other access is in progress.
Step 2 The processor writes data A to the cache, re-
sulting in a write miss. Therefore, the data is put
into the write buffers, assuming they are not full.
No external access can be started because
AHOLD is still 1.
R2
BOFF
Data
HITM
EADS
INV
AHOLD
R1
BRDY
BLAST
ADS
W/R
M/IO
CACHE
ADR
CLK
W1 to CPU
don’t care
W1
W2
W3
W4
W1 from CPU
W3
W4
Figure 13. Cycle Reordering with BOFF (Write-Back)
Note:
The circled numbers in this figure represent the steps in section 4.8.6.
W2
11
12
R2 from CPU
R1 from CPU
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