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參數(shù)資料
| 型號： | AM5X86 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能單片32位微處理器) |
| 中文描述： | 高性能設計的片上集成完整的32位架構Micrprocessor（高性能單片32位微處理器） |
| 文件頁數(shù)： | 56/67頁 |
| 文件大?。?/td> | 1201K |
| 代理商： | AM5X86 |
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56
Am5
X
86 Microprocessor
AMD
Am5
X
86 CPU IDENTIFICATION
The Am5
X
86 microprocessor supports two standard
methods for identifying the CPU in a system. The re-
ported values are assigned based on the RESET status
of the WB/WT pin input (Low = write-through; High =
write-back).
PRELIMINARY
10
10.1 DX Register at RESET
The DX register always contains a component identifier
at the conclusion of RESET. The upper byte of DX (DH)
contains 04 and the lower byte of DX (DL) contains a
CPU type/stepping identifier (see Table 19).
10.2 CPUID Instruction
The Am5
X
86 microprocessor family implements the
CPUID instruction that makes information available to
software about the family, model and stepping of the
microprocessor on which it is executing. Support of this
instruction is indicated by the presence of a user-mod-
ifiable bit in position EFLAGS.21, referred to as the
EFLAGS.ID bit. This bit is reset to zero at device reset
(RESET or SRESET) for compatibility with existing pro-
cessor designs.
10.2.1 CPUID Timing
CPUID execution timing depends on the selected EAX
parameter values (see Table 20).
10.2.2 CPUID Operation
The CPUID instruction requires the user to pass an input
parameter to the CPU in the EAX register. The CPU
response is returned to the user in registers EAX, EBX,
ECX, and EDX.
When the parameter passed in EAX is zero, the register
values returned upon instruction execution are:
The values in EBX, ECX, and EDX indicate an AMD
microprocessor. When taken in the proper order:
I
EBX (least significant bit to most significant bit)
I
EDX (least significant bit to most significant bit)
I
ECX (least significant bit to most significant bit)
they decode to
AuthenticAMD
When the parameter passed in EAX is 1, the register
values returned are:
EAX[3:0]
Stepping ID*
EAX[7:4]
model:
Am5
X
86 CPU:
Write-through mode = Eh
Write-back mode = Fh
Family
486 Instruction Set = 4h
EAX[15:12]
0000
EAX[31:16]
RESERVED
EBX[31:0]
00000000h
ECX[31:0]
00000000h
EDX[31:0]
00000001h = all versions
The 1 in bit 0 indicates that the FPU
is present
Note:
*Please contact AMD at (800) 222-9323
for stepping ID details.
The value returned in EAX after CPUID instruction ex-
ecution is identical to the value loaded into EDX upon
device reset. Software must avoid any dependency
upon the state of reserved processor bits.
When the parameter passed in EAX is greater than one,
register values returned upon instruction execution are:
Table 19. CPU ID Codes
CLKMUL Setting/Cache mode
Component
ID (DH)
Revision
ID (DL)
Write-through mode
04
Ex
Write-back mode
04
Fx
Table 20. CPUID Instruction Description
OP
Code
Instruction
EAX
Input
Value
0
1
>1
CPU
Core
Clocks
41
14
9
Description
0F A2 CPUID
AMD string
CPU ID Register
null registers
EAX[31:0]
EBX[31:0]
ECX[31:0]
EDX[31:0]
00000001h
68747541h
444D4163h
69746E65h
EAX[11:8]
EAX[31:0]
EBX[31:0]
ECX[31:0]
EDX[31:0]
Flags affected
: No flags are affected.
Exceptions
: None
00000000h
00000000h
00000000h
00000000h
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