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參數(shù)資料
| 型號： | AM42BDS640AG |
| 廠商： | Spansion Inc. |
| 元件分類： | SRAM |
| 英文描述： | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| 中文描述： | 堆疊式多芯片封裝（MCP）閃存和SRAM |
| 文件頁數(shù)： | 64/72頁 |
| 文件大?。?/td> | 1060K |
| 代理商： | AM42BDS640AG |
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66
Am42BDS640AG
November 1, 2002
P R E L I M INARY
SRAM AC CHARACTERISTICS
Notes:
1. CE1#s controlled.
2. t
CW is measured from CE1#s going low to the end of write.
3. t
WR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. tAS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (t
WP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
WP is measured from the beginning of write
to the end of write.
Figure 37.
SRAM Write Cycle—CE1#s Control
Address
Data Valid
UB#s, LB#s
WE#
Data In
Data Out
High-Z
tWC
CE1#s
CE2s
tAW
tAS (See Note 2)
tBW
tCW
(See Note 3)
tWR (See Note 4)
tWP
(See Note 5)
tDW
tDH
(See Note 6)
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| AM42BDS640AGBC8IS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
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| AM42BDS640AGBC9IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM42BDS640AGBD8IS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
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