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參數(shù)資料
| 型號(hào)： | AM29BDS640GTD8WSI |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 4M X 16 FLASH 1.8V PROM, 14 ns, PBGA80 |
| 封裝： | 11 X 12 MM, 0.80 MM PITCH, FBGA-80 |
| 文件頁數(shù)： | 60/65頁 |
| 文件大?。?/td> | 899K |
| 代理商： | AM29BDS640GTD8WSI |
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October 31, 2002
Am29BDS640G
59
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Wait State Decoding Addresses:
A14, A13, A12 = “101”
5 programmed, 7 total
A14, A13, A12 = “100”
4 programmed, 6 total
A14, A13, A12 = “011”
3 programmed, 5 total
A14, A13, A12 = “010”
2 programmed, 4 total
A14, A13, A12 = “001”
1 programmed, 3 total
A14, A13, A12 = “000”
0 programmed, 2 total
Note:
Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to “101”.
Figure 32.
Example of Wait States Insertion (Standard Handshaking Device)
Data
AVD#
OE#
CLK
1
2
3
4
5
D0
D1
0
1
6
2
7
3
total number of clock cycles
following AVD# falling edge
Rising edge of next clock cycle
following last wait state triggers
next burst data
number of clock cycles
programmed
4
5
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