參數(shù)資料
型號(hào)： AM29BDS640GTD8WSI
廠商： SPANSION LLC
元件分類： DRAM
英文描述： 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
中文描述： 4M X 16 FLASH 1.8V PROM, 14 ns, PBGA80
封裝： 11 X 12 MM, 0.80 MM PITCH, FBGA-80
文件頁(yè)數(shù)： 14/65頁(yè)
文件大?。?/td> 899K
代理商： AM29BDS640GTD8WSI
October 31, 2002
Am29BDS640G
13
A D V A N C E I N F O R M A T I O N
read mode, active clock edge, RDY configuration, and
synchronous mode active.
Reduced Wait-State Handshaking Option
The device can be equipped with a reduced wait-state
handshaking feature that allows the host system to
simply monitor the RDY signal from the device to deter-
mine when the initial word of burst data is ready to be
read. The host system should use the programmable
wait state configuration to set the number of wait states
for optimal burst mode operation. The initial word of
burst data is indicated by the rising edge of RDY after
OE# goes low.
The presence of the reduced wait-state handshaking
feature may be verified by writing the autoselect
command sequence to the device. See “Autoselect
Command Sequence” for details.
For optimal burst mode performance on devices
without the reduced wait-state handshaking option, the
host system must set the appropriate number of wait
states in the flash device depending on clock frequency
and the presence of a boundary crossing. See
“Set
Burst Mode Configuration Register Command
Sequence” section on page 22
section for more infor-
mation. The device will automatically delay RDY and
data by one additional clock cycle when the starting
address is odd.
The autoselect function allows the host system to
determine whether the flash device is enabled for
reduced wait-state handshaking. See the “Autoselect
Command Sequence” section for more information.
Simultaneous Read/Write Operations with
Zero Latency
This device is capable of reading data from one bank
of memory while programming or erasing in another
bank of memory. An erase operation may also be sus-
pended to read from or program to another location
within the same bank (except the sector being erased).
Figure 33, “Back-to-Back Read/Write Cycle Timings,”
on page 60
shows how read and write cycles may be
initiated for simultaneous operation with zero latency.
Refer to the DC Characteristics table for
read-while-program and read-while-erase current
specifications.
Writing Commands/Command Sequences
The device has the capability of performing an asyn-
chronous or synchronous write operation. During a
synchronous write operation, to write a command or
command sequence (which includes programming
data to the device and erasing sectors of memory), the
system must drive AVD# and CE# to V
IL
, and OE# to
V
IH
when providing an address to the device, and drive
WE# and CE# to V
IL
, and OE# to V
IH
. when writing
commands or data. During an asynchronous write
operation, the system must drive CE#, WE#, and CLK
to V
IL
and OE# to V
IH
when providing an address, com-
mand, and data. The asynchronous and synchronous
programing operation is independent of the Set Device
Read Mode bit in the Burst Mode Configuration Reg-
ister.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a word, instead of four.
An erase operation can erase one sector, multiple sec-
tors, or the entire device.
Table 8, “Programmable Wait
State Settings,” on page 23
indicates the address
space that each sector occupies. The device address
space is divided into four banks: Banks B and C contain
only 32 Kword sectors, while Banks A and D contain
both 8 Kword boot sectors in addition to 32 Kword sec-
tors. A “bank address” is the address bits required to
uniquely select a bank. Similarly, a “sector address” is
the address bits required to uniquely select a sector.
I
CC2
in the DC Characteristics table represents the
active current specification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. ACC is primarily intended to
allow faster manufacturing throughput at the factory.
If the system asserts V
ID
on this input, the device auto-
matically enters the aforementioned Unlock Bypass
mode and uses the higher voltage on the input to
reduce the time required for program operations. The
system would use a two-cycle program command
sequence as required by the Unlock Bypass mode.
Removing V
ID
from the ACC input returns the device to
normal operation. Note that sectors must be unlocked
prior to raising ACC to V
ID
.
Note that the ACC pin must
not be at V
ID
for operations other than accelerated pro-
gramming, or device damage may result. In addition,
the ACC pin must not be left floating or unconnected;
inconsistent behavior of the device may result
.
When at V
IL
, ACC locks all sectors. ACC should be at
V
IH
for all other conditions.
Autoselect Functions
If the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ15–DQ0. Autoselect mode may only be
entered and used when in the asynchronous read
mode. Refer to the
“Autoselect Command Sequence”
section on page 25
section for more information.
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