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參數(shù)資料
| 型號： | ALC202 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:100; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:22; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:22-35 RoHS Compliant: No |
| 中文描述： | AC\u0026#39;97音頻編解碼器 |
| 文件頁數(shù)： | 25/29頁 |
| 文件大?。?/td> | 598K |
| 代理商： | ALC202 |
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Preliminary
Avance Logic, Inc.
ALC202
-
25 -
Rev0.62
http://www.realtek.com.tw
Parameter
Symbol
Trise
clk
Tfall
clk
Trise
sync
Tfall
sync
Trise
din
Tfall
din
Trise
dout
Tfall
dout
Min
-
-
-
-
-
-
-
-
Typ
-
-
-
-
-
-
-
-
Max
6
6
6
6
6
6
6
6
Units
ns
ns
ns
ns
ns
ns
ns
ns
BIT_CLK rise time
BIT_CLK fall time
SYNC rise time
SYNC fall time
SDATA_IN rise time
SDATA_IN fall time
SDATA_OUT rise time
SDATA_OUT fall time
Note 1: 75pF external load (50 pF in AC’97 rev2.1)
Note 2: rise is from 10% to 90% of Vdd (V
ol
to V
oh
)
Note 3: fall is from 90% to 10% of Vdd (V
oh
to V
ol
)
6.2.6 AC-Link Low Power Mode Timing:
Fig 6.2.6-1 AC-Link low power mode timing diagram
Parameter
Symbol
T
s2_pdown
Min
-
Typ
-
Max
1.0
Units
us
End of slot 2 to BIT_CLK,
SDATA_IN low
6.2.7 ATE Test Mode:
Fig 6.2.6-1 ATE test mode timing diagram
*To meet AC’97 rev2.2, there are EAPD, SPDIFO, BIT_CLK and SDATA_IN should be floating in
test mode.
Parameter
Symbol
Setup to trailing edge of
RESET# (also applies to SYNC)
Rising edge of RESET# to Hi-Z
delay
Min
15.0
Typ
-
Max
-
Units
ns
T
setup2rst
T
off
-
-
25.0
ns
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|---|---|
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