參數(shù)資料
型號(hào)： ALC202
廠商： Electronic Theatre Controls, Inc.
元件分類： 圓形連接器
英文描述： Circular Connector; No. of Contacts:100; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:22; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:22-35 RoHS Compliant: No
中文描述： AC\u0026#39;97音頻編解碼器
文件頁(yè)數(shù)： 18/29頁(yè)
文件大?。?/td> 598K
代理商： ALC202
Preliminary
Avance Logic, Inc.
ALC202
-
18 -
Rev0.62
http://www.realtek.com.tw
5. Design Suggestion
5.1 Clocking
The clock source of different configuration is listed below:
CODEC ID[1..0]
BIT-CLK
(12.288MHz)
00
Clock source
Output
24.576M/14.318M crystal or external clock
source input from XTAL-IN*
12.288MHz clock input from BIT-CLK
12.288MHz clock input from BIT-CLK
12.288MHz clock input from BIT-CLK
01
10
11
Input
Input
Input
*The default clock source should be decided by XTLSEL, once 14.318MHz clock is selected,
internal digital PLL transfers it into 24.576MHz clock.
5.2 AC-Link
When ALC202 take serial data from AC97 controller, it sample
SDATA_OUT
on the falling
edge of
BIT_CLK
.When ALC202 send serial data to AC97 controller, it start to drive
SDATA_IN
on
the rising edge of
BIT_CLK.
ALC202 will return any uninstalled bits or registers with 0 for read operation.. ALC202 also
stuff the unimplemented slot or bit with 0 in
SDATA-IN
. Note that AC-LINK is MSB-justified.
Refer to “
Audio CODEC ’97 Component Specification Revision 2.1/2.2”
for detail.
0
1
2
3
4
5
6
7
8
9
10
11
12
TAG
CMD DATA PCM
L
PCMR
SPDIF
L
SPDIF
R
TAG ADDR DATA PCM
L
PCMR
Fig5.2-1 Default ALC202 slot arrangement – CODEC ID = 00
0
1
2
3
4
5
6
7
8
9
10
11
12
TAG
CMD DATA
SPDIF
L
PCM
L
PCMR SPDIF
R
TAG ADDR DATA PCM
L
PCMR
Fig5.2-2 Default ALC202 slot arrangement – CODEC ID = 01, 10
0
1
2
3
4
5
6
7
8
9
10
11
12
TAG
CMD DATA
PCM
L
PCMR SPDIF
L
SPDIF
R
TAG ADDR DATA PCM
L
PCMR
Slot#
SYNC
SDATA-OUT
SDATA-IN
Slot#
SYNC
SDATA-OUT
SDATA-IN
Slot#
SYNC
SDATA-OUT
SDATA-IN
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