參數(shù)資料
型號(hào)： ALC202
廠商： Electronic Theatre Controls, Inc.
元件分類： 圓形連接器
英文描述： Circular Connector; No. of Contacts:100; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:22; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:22-35 RoHS Compliant: No
中文描述： AC\u0026#39;97音頻編解碼器
文件頁(yè)數(shù)： 15/29頁(yè)
文件大?。?/td> 598K
代理商： ALC202
Preliminary
Avance Logic, Inc.
ALC202
-
15 -
Rev0.62
http://www.realtek.com.tw
software doesn’t keep the same sample rates, the S/PDIF output will be auto forbidden by hardware,
and undefined consequence may be occurred.
Extension Registers:
MX76
GPIO Setup
Type
R/W
GPIO Statue Indication in SDATA_IN
0:The status of GPIO0/GPIO1/JD and its valid tag are not indicated in
SDATA_IN.
1: The status of GPIO0/GPIO1/JD and its valid tag are indicated in SDATA_IN
Reserved
R/W
JD (Jack-Detect) interrupt Enable (when pin-47 is used as Jack-Detect)
0: Disable 1: Enable.
A low to high transaction will trigger the JD interrupt in bit0 of SDATA_IN’s
slot-12.
R/W
GPIO1 interrupt Enable (when GPIO1 is used as input)
0: Disable 1: Enable.
A low to high transaction will trigger the GPIO interrupt in bit0 of SDATA_IN’s
slot-12.
R/W
GPIO0 interrupt Enable (when GPIO0 is used as input)
0: Disable 1: Enable.
A low to high transaction will trigger the GPIO interrupt in bit0 of SDATA_IN’s
slot-12.
Reserved
R/W
GPIO1Primitiveness Control
0: Set GPIO1 as input pin.
1: Set GPIO1 as output pin.
R/W
GPIO0 Primitiveness Control
0: Set GPIO0 as input pin.
1: Set GPIO0 as output pin.
Software programmer can enable JD interrupt to know the “Jack Detection” event occurs.
The Bit-Allocation of GPIO/JD status in AC-LINK:
Default: 0000h
Function
Bit
15
14:6
6
5
4
3:2
1
0
*GPINT = (MX78.6 | MX78.5 | MX78.4)
MX78
GPIO Status
Type
Default: 0000h
Function
Bit
Frame Addr
Data PCML PCMR
GPIO
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SYNC
SDATA-IN
(Slot-0)
SDATA-IN
(Slot-12)
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIO1 GPIO0 GPINT
GPINT
JD
相關(guān)PDF資料
PDF描述
ALD4701 QUAD MICOPOWER RAIL TO RAIL CMOS OPERATIOANAL AMPLIFIER
ALD4701A QUAD MICOPOWER RAIL TO RAIL CMOS OPERATIOANAL AMPLIFIER
ALD4701ADB QUAD MICOPOWER RAIL TO RAIL CMOS OPERATIOANAL AMPLIFIER
ALD4701APB QUAD MICOPOWER RAIL TO RAIL CMOS OPERATIOANAL AMPLIFIER
ALD4701ASB QUAD MICOPOWER RAIL TO RAIL CMOS OPERATIOANAL AMPLIFIER
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