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參數(shù)資料
| 型號： | AK4704 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 2ch 24bit DAC with AV SCART switch |
| 中文描述： | 2通道24位DAC，具有影音SCART開關(guān) |
| 文件頁數(shù)： | 29/44頁 |
| 文件大小： | 440K |
| 代理商： | AK4704 |
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
Rev. 0.5
2004/1
- 29 -
6. Control Interface
I
2
C-bus Control Mode
1. WRITE Operations
Figure 9 shows the data transfer sequence in I
2
C-bus mode. All commands are preceded by a START condition. A HIGH
to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 15). After the START
condition, a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction bit (R/W).
The most significant seven bits of the slave address are fixed as “0010001”. If the slave address match that of the
AK4704, the AK4704 generates the acknowledge and the operation is executed. The master must generate the
acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 16). A
“1” for R/W bit indicates that the read operation is to be executed. A “0” indicates that the write operation is to be
executed. The second byte consists of the address for control registers of the AK4704. The format is MSB first, and those
most significant 3-bits are fixed to zeros (Figure 11). The data after the second byte contain control data. The format is
MSB first, 8bits (Figure 12). The AK4704 generates an acknowledge after each byte has been received. A data transfer is
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition (Figure 15).
The AK4704 can execute multiple one byte write operations in a sequence. After receipt of the third byte, the AK4704
generates an acknowledge, and awaits the next data again. The master can transmit more than one byte instead of
terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal address
counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 09H prior
to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW (Figure 17) except for the START and the STOP
condition.
S
T
A
R
T
Slave
Address
Address(n)
SDA
A
C
K
A
C
K
S
A
C
K
Sub
Data(n)
P
S
T
O
P
Data(n+x)
A
C
K
Data(n+1)
A
C
K
R/W= “0”
A
C
K
Figure 9. Data transfer sequence at the I
2
C-bus mode
0
0
1
0
0
0
1
R/W
Figure 10. The first byte
0
0
0
A4
A3
A2
A1
A0
Figure 11. The second byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 12. Byte structure after the second byte
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