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參數(shù)資料
| 型號： | AK4704 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 2ch 24bit DAC with AV SCART switch |
| 中文描述： | 2通道24位DAC，具有影音SCART開關(guān) |
| 文件頁數(shù)： | 23/44頁 |
| 文件大?。?/td> | 440K |
| 代理商： | AK4704 |
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
Rev. 0.5
2004/1
- 23 -
Zero-cross Detection and Offset Calibration
To minimize the click noise at changing the gain of volume #1, the AK4704 has a zero-cross detection and an offset
calibration function. When DAPD bit =”1”, the zero-cross detection and offset calibration does not work.
1. Zero-cross detection function (03H: D2-D0)
When the ZERO bit = “1”, the zero-cross detection function is enabled. The gain of volume #1 changes at the first
zero-cross point from the acknowledgement of a volume changing command or when the zero-cross is not detected within
the time set by ZTM1-0 bits (256/fs to 2048/fs). The zero-cross counter is initialized whenever a gain is issued. The
zero-cross is detected on L/R channels independently. To disable this function, set the ZERO bit to “0”.
ZERO: Zero-cross detection enable for volume #1
0 : Disable. The volume value changes immediately without zero-cross.
1 : Enable (default). The volume value changes at a zero-crossing point or when timeout (ZTM1-0 bit
setting) occurs.
The internal comparator for zero-cross detection has a small offset. Therefore, the gain of volume #1 may change due to
a zero-cross timeout before the comparator-based zero-cross detection occurs.
When the new gain value 1EH(-2dB) is written while the gain of both Lch and Rch are 1FH(0dB), if the Lch detects the
zero-cross prior to Rch, only the gain of Lch changes to 1EH(-2dB) while Rch waits for a zero-cross. After that, if the gain
is set to 1DH(-4dB) before either a zero-cross or zero-cross timeout, the Rch keeps the same value and changes from 1FH
to 1DH at next zero-cross or timeout.
WR[Gain=1EH]
WR[Gain=1DH]
1FH
Lch Gain
Rch Gain
Gain Registers
Zero-cross
1FH
1EH
1DH
1DH
1EH
1FH
1DH
zero-cross timer initialized
Timeout;
(may have click noise)
Timer (256/fs to2048/fs)
Figure 7. Zero-cross Operation (ZERO= “1”)
2. Offset calibration function (03H: D5)
Offset calibration is enabled when the CAL bit = “1”. This function begins when the TVOUT source is switched to DAC
after the STBY bit is changed to “0”. It takes 1664/fs to execute the offset calibration cycle. During the offset calibration
cycle, the analog outputs are muted. Once the offset calibration is executed, the calibration memory is held until PDN pin
= “L” or the new calibration is executed. When the switch is changed from DAC to VCR during calibration, the
calibration is discontinued, and resumed when TVOUT is switched back to DAC. If volume #1 gain is changed during
calibration, the change takes place after calibration is complete.
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