參數(shù)資料
型號(hào): AK4704
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 2ch 24bit DAC with AV SCART switch
中文描述: 2通道24位DAC,具有影音SCART開關(guān)
文件頁數(shù): 13/44頁
文件大小: 440K
代理商: AK4704
ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
Rev. 0.5
2004/1
- 13 -
SWITCHING CHARACTERISTICS
(Ta = 25
°
C; VP=11.4
12.6V, VD = 4.75
5.25V, VVD1=VVD2 = 4.75
5.25V; C
L
= 20pF)
Parameter
Master Clock Frequency 256fs:
Duty Cycle
384fs:
Duty Cycle
LRCK Frequency
Duty Cycle
Audio Interface Timing
BICK Period
BICK Pulse Width Low
Pulse Width High
BICK “
” to LRCK Edge (Note: 17)
LRCK Edge to BICK “
” (Note: 17)
SDTI Hold Time
SDTI Setup Time
Control Interface Timing (I
2
C Bus):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note: 18)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise
Suppressed by Input Filter
Reset Timing
PDN Pulse Width (Note: 19)
Note: 17. BICK rising edge must not occur at the same time as LRCK edge.
Note: 18. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note: 19. The AK4704 should be reset by PDN= “L” upon power up.
Note: 20. I
2
C is a registered trademark of Philips Semiconductors.
Purchase of Asahi Kasei Microsystems Co., Ltd I
2
C components conveys a license under the Philips I
2
C patent
to use the components in the I
C system, provided the system conform to the I
C specifications defined by
Philips.
Symbol
fCLK
dCLK
fCLK
dCLK
fs
Duty
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
Min
2.048
40
3.072
40
8
45
312.5
100
100
50
50
50
50
-
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
0.6
0
typ
max
12.8
60
19.2
60
50
55
Units
MHz
%
MHz
%
kHz
%
ns
ns
ns
ns
ns
ns
ns
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
400
-
-
-
-
-
-
-
0.3
0.3
-
50
tPD
150
ns
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