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參數(shù)資料
| 型號(hào)： | AK4683 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | Asynchronous Multi-Channel Audio CODEC with DIR/T |
| 中文描述： | 異步多聲道音頻編解碼器署長/噸 |
| 文件頁數(shù)： | 60/82頁 |
| 文件大小： | 1257K |
| 代理商： | AK4683 |
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ASAHI KASEI
[AK4683]
MS0427-E-01
2005/11
- 60 -
(2). I
2
C bus control mode (I2C pin = “H”)
AK4683 supports the standard-mode I
2
C-bus (max: 100kHz). Then AK4683 does not support a fast-mode I
2
C-bus
system (max: 400kHz).
(2)-1. Data transfer
All commands are preceded by a START condition. After the START condition, a slave address is sent. After the
AK4683 recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted
over the SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave
device pulls the SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by a STOP condition
generated by the master device.
(2)-1-1. Data validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW except for the START and the STOP condition.
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 41. Data transfer
(2)-1-2. START and STOP condition
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. All sequences start from
the START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. All sequences end by the
STOP condition.
SCL
SDA
STOP CONDITION
START CONDITION
Figure 42. START and STOP conditions
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