參數(shù)資料
型號(hào)： AK4683
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類(lèi)： Codec
英文描述： Asynchronous Multi-Channel Audio CODEC with DIR/T
中文描述： 異步多聲道音頻編解碼器署長(zhǎng)/噸
文件頁(yè)數(shù)： 41/82頁(yè)
文件大?。?/td> 1257K
代理商： AK4683
ASAHI KASEI
[AK4683]
MS0427-E-01
2005/11
- 41 -
Power ON/OFF Sequence
The each block of the AK4683 are placed in the power-down mode by bringing PDN pin “L” and both digital filters are
reset at the same time. PDN pin “L” also reset the control registers to their default values. In the power-down mode, the
analog outputs go to VCOM voltage and SDTOA,B, DZF/OVF pin go to “L”. This reset should always be done after
power-up.
In slave mode, after exiting reset at power-up etc., the AK4683 starts to operate from the rising edge of LRCK after
MLCK, then the device is in the power-down mode until MCLK and LRCK are input. In slave mode or Internal Loop
Mode, the AK4683 starts to operate by the input of MLCK after exiting reset.
The analog initialization cycle of ADC starts after exiting the power-down mode. Therefore, the output data, SDTO
becomes available after 522/fs cycles of LRCK clock. In case of the DAC, an analog initialization cycle starts after
exiting the power-down mode. The analog outputs are VCOM voltage during the initialization. Figure 23 hows the
sequences of the power-down and the power-up.
The ADC and all DACs can be powered-down individually by PWAD bit and PWDA1-2 bits. These bits don’t initialize
the internal register values. When PWAD bit = “0” and selecting ADC, the SDTOA(SDTOB) pin goes to “L”. When
PWDA1-2 bits = “0”, the analog outputs go to VCOM voltage and DZF/OVF pin go to “H”. Since some click noise
may occur, the analog output should muted externally if the click noise influences system application.
Power
ADC Internal
State
PDN
Clock In
MCLK,LRCK,SCLK
ADC In
(Analog)
ADC Out
(Digital)
DAC Internal
State
DAC In
(Digital)
DAC Out
(Analog)
External
Mute
Mute ON
(9)
DZF1/DZF2
Power-down
Don’t care
GD
“0”data
Power-down
“0”data
GD
(3)
(3)
(4)
(6)
(7)
(8)
522/fs
Init Cycle
Normal Operation
(1)
GD
Normal Operation
GD
(5)
(6)
516/fs
Init Cycle
(2)
10
～
11/fs (10)
Mute ON
“0”data
“0”data
Don’t care
Notes:
(1) The analog part of ADC is initialized after exiting the power-down state.
(2) The analog part of DAC is initialized after exiting the power-down state.
(3) Digital output corresponding to analog input and analog output corresponding to digital input have the group
delay (GD).
(4) ADC output is “0” data at the power-down state.
(5) Click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if the
click noise influences system application.
(6) Click noise occurs at the falling edge of PDN and at 512/fs(DAC1) and 512/fs +96ms(DAC2) after the rising
edge of PDN.
(7) When the external clocks
(MCLK, BICKA (BICKB), LRCKA (LRCKB))
are stopped, the AK4683 should be in the
power-down mode.
(8) DZF/OVF pin is “L” in the power-down mode (PDN pin = “L”).
(9) Please mute the analog output externally if the click noise (6) influences system application.
(10) DZF pin = “L” for 10
～
11/fs after PDN= “
↑
”.
Figure 23. Power-down/up sequence example
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